SHA512H

SHA512 Hash update part 1 takes the values from the three 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the sigma1 and chi functions of two iterations of the SHA512 computation. It returns this value to the destination SIMD&FP register.

This instruction is implemented only when ARMv8.2-SHA is implemented.

Advanced SIMD
(ARMv8.2)

313029282726252423222120191817161514131211109876543210
11001110011Rm100000RnRd

Advanced SIMD

SHA512H <Qd>, <Qn>, <Vm>.2D

if !HaveSHA512Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm);

Assembler Symbols

<Qd>

Is the 128-bit name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Qn>

Is the 128-bit name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vtmp; bits(64) MSigma1; bits(64) tmp; bits(128) X = V[n]; bits(128) Y = V[m]; bits(128) W = V[d]; MSigma1 = ROR(Y<127:64>, 14) EOR ROR(Y<127:64>,18) EOR ROR(Y<127:64>,41); Vtmp<127:64> = (Y<127:64> AND X<63:0>) EOR (NOT(Y<127:64>) AND X<127:64>); Vtmp<127:64> = (Vtmp<127:64> + MSigma1 + W<127:64>); tmp = Vtmp<127:64> + Y<63:0>; MSigma1 = ROR(tmp, 14) EOR ROR(tmp,18) EOR ROR(tmp,41); Vtmp<63:0> = (tmp AND Y<127:64>) EOR (NOT(tmp) AND X<63:0>); Vtmp<63:0> = (Vtmp<63:0> + MSigma1 + W<63:0>); V[d] = Vtmp;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.25, AdvSIMD v27.01, pseudocode v85-xml-00bet8_rc3 ; Build timestamp: 2018-09-13T13:04

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