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SUBSS—Subtract Scalar Single-Precision Floating-Point Value

Opcode/Instruction Op /En 64/32 bit Mode Support CPUID Feature Flag Description

F3 0F 5C /r

SUBSS xmm1, xmm2/m32

RM V/V SSE Subtract the low single-precision floating-point value in xmm2/m32 from xmm1 and store the result in xmm1.

VEX.NDS.128.F3.0F.WIG 5C /r

VSUBSS xmm1,xmm2, xmm3/m32

RVM V/V AVX Subtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1.


VSUBSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}

T1S V/V AVX512F Subtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1 under writemask k1.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RM ModRM:reg (r, w) ModRM:r/m (r) NA NA
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA


Subtract the low single-precision floating-point value from the second source operand and the first source operand and store the double-precision floating-point result in the low doubleword of the destination operand.

The second source operand can be an XMM register or a 32-bit memory location. The first source and destination operands are XMM registers.

128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged.

VEX.128 and EVEX encoded versions: Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.

EVEX encoded version: The low doubleword element of the destination operand is updated according to the writemask.

Software should ensure VSUBSS is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.


VSUBSS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
IF k1[0] or *no writemask*
    DEST[31:0] (cid:197) SRC1[31:0] - SRC2[31:0]
    IF *merging-masking*
        ; merging-masking
        THEN *DEST[31:0] remains unchanged*
        ; zeroing-masking
        THEN DEST[31:0] (cid:197) 0
DEST[127:32] (cid:197) SRC1[127:32]
DEST[MAX_VL-1:128] (cid:197) 0
VSUBSS (VEX.128 encoded version)
DEST[31:0] (cid:197)SRC1[31:0] - SRC2[31:0]
DEST[127:32] (cid:197)SRC1[127:32]
DEST[MAX_VL-1:128] (cid:197)0
SUBSS (128-bit Legacy SSE version)
DEST[31:0] (cid:197)DEST[31:0] - SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VSUBSS __m128 _mm_mask_sub_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);
VSUBSS __m128 _mm_maskz_sub_ss (__mmask8 k, __m128 a, __m128 b);
VSUBSS __m128 _mm_sub_round_ss (__m128 a, __m128 b, int);
VSUBSS __m128 _mm_mask_sub_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VSUBSS __m128 _mm_maskz_sub_round_ss (__mmask8 k, __m128 a, __m128 b, int);
SUBSS __m128 _mm_sub_ss (__m128 a, __m128 b);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions

VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.