CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value

NOTES: 1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Description

Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from” source operand to a single-precision floating-point value in the destination operand (first operand). The “convert-from” source operand can be a general-purpose register or a memory location. The destination operand is an XMM register. The result is stored in the low doubleword of the destination operand, and the upper three doublewords are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits.

128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input value. The “convert-from” source operand (the second operand) is a general-purpose register or memory location. Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged.

VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a general-purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.

EVEX encoded version: the converted result in written to the low doubleword element of the destination under the writemask.

Software should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter unpredictable behavior across different processor generations.

Operation

IF (SRC2 *is register*) AND (EVEX.b = 1)
    THEN
    SET_RM(EVEX.RC);
    ELSE
    SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
    THEN
    DEST[31:0] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
    ELSE
    DEST[31:0] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] (cid:197) SRC1[127:32]
DEST[MAX_VL-1:128] (cid:197) 0

IF 64-Bit Mode And OperandSize = 64
    THEN
    DEST[31:0] (cid:197)Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
    ELSE
    DEST[31:0] (cid:197)Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] (cid:197)SRC1[127:32]
DEST[MAX_VL-1:128] (cid:197)0

IF 64-Bit Mode And OperandSize = 64
    THEN
    DEST[31:0] (cid:197)Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
    ELSE
    DEST[31:0] (cid:197)Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[MAX_VL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSI2SS __m128 _mm_cvti32_ss(__m128 s, int a);
VCVTSI2SS __m128 _mm_cvt_roundi32_ss(__m128 s, int a, int r);
VCVTSI2SS __m128 _mm_cvti64_ss(__m128 s, __int64 a);
VCVTSI2SS __m128 _mm_cvt_roundi64_ss(__m128 s, __int64 a, int r);
CVTSI2SS __m128 _mm_cvtsi64_ss(__m128 s, __int64 a);
CVTSI2SS __m128 _mm_cvtsi32_ss(__m128 a, int b);

SIMD Floating-Point Exceptions

Precision

Other Exceptions