| Opcode/Instruction | Op En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
| VEX.L0.0F.W0 99 /r KTESTW k1, k2 | RR | V/V | AVX512DQ | Set ZF and CF depending on sign bit AND and ANDN of 16 bits mask register sources. |
| VEX.L0.66.0F.W0 99 /r KTESTB k1, k2 | RR | V/V | AVX512DQ | Set ZF and CF depending on sign bit AND and ANDN of 8 bits mask register sources. |
| VEX.L0.0F.W1 99 /r KTESTQ k1, k2 | RR | V/V | AVX512BW | Set ZF and CF depending on sign bit AND and ANDN of 64 bits mask register sources. |
| VEX.L0.66.0F.W1 99 /r KTESTD k1, k2 | RR | V/V | AVX512BW | Set ZF and CF depending on sign bit AND and ANDN of 32 bits mask register sources. |
Op/En
Operand 1
Operand2
RR
ModRM:reg (r)
ModRM:r/m (r, ModRM:[7:6] must be 11b)
Performs a bitwise comparison of the bits of the first source operand and corresponding bits in the second source operand. If the AND operation produces all zeros, the ZF is set else the ZF is clear. If the bitwise AND operation of the inverted first source operand with the second source operand produces all zeros the CF is set else the CF is clear. Only the EFLAGS register is updated.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
KTESTW
TEMP[15:0] (cid:197) SRC2[15:0] AND SRC1[15:0]
IF (TEMP[15:0] = = 0)
THEN ZF (cid:197)1;
ELSE ZF (cid:197) 0;
FI;
TEMP[15:0] (cid:197) SRC2[15:0] AND NOT SRC1[15:0]
IF (TEMP[15:0] = = 0)
THEN CF (cid:197)1;
ELSE CF (cid:197) 0;
FI;
AF (cid:197) OF (cid:197) PF (cid:197) SF (cid:197) 0;
KTESTB
TEMP[7:0] (cid:197) SRC2[7:0] AND SRC1[7:0]
IF (TEMP[7:0] = = 0)
THEN ZF (cid:197)1;
ELSE ZF (cid:197) 0;
FI;
TEMP[7:0] (cid:197) SRC2[7:0] AND NOT SRC1[7:0]
IF (TEMP[7:0] = = 0)
THEN CF (cid:197)1;
ELSE CF (cid:197) 0;
FI;
AF (cid:197) OF (cid:197) PF (cid:197) SF (cid:197) 0;
KTESTQ
TEMP[63:0] (cid:197) SRC2[63:0] AND SRC1[63:0]
IF (TEMP[63:0] = = 0)
THEN ZF (cid:197)1;
ELSE ZF (cid:197) 0;
FI;
TEMP[63:0] (cid:197) SRC2[63:0] AND NOT SRC1[63:0]
IF (TEMP[63:0] = = 0)
THEN CF (cid:197)1;
ELSE CF (cid:197) 0;
FI;
AF (cid:197) OF (cid:197) PF (cid:197) SF (cid:197) 0;
KTESTD
TEMP[31:0] (cid:197) SRC2[31:0] AND SRC1[31:0]
IF (TEMP[31:0] = = 0)
THEN ZF (cid:197)1;
ELSE ZF (cid:197) 0;
FI;
TEMP[31:0] (cid:197) SRC2[31:0] AND NOT SRC1[31:0]
IF (TEMP[31:0] = = 0)
THEN CF (cid:197)1;
ELSE CF (cid:197) 0;
FI;
AF (cid:197) OF (cid:197) PF (cid:197) SF (cid:197) 0;
None
See Exceptions Type K20.