| Opcode | Instruction | Op/En | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|---|
| 0F 03 /r | LSL r16, r16/m16 | RM | Valid | Valid | Load: r16 ← segment limit, selector r16/m16. |
| 0F 03 /r | LSL r32, r32/m16* | RM | Valid | Valid | Load: r32 ← segment limit, selector r32/m16. |
| REX.W + 0F 03 /r | LSL r64, r32/m16* | RM | Valid | Valid | Load: r64 ← segment limit, selector r32/m16 |
NOTES:
*For all loads (regardless of destination sizing), only bits 16-0 are used. Other bits are ignored.
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| RM | ModRM:reg (w) | ModRM:r/m (r) | NA | NA |
Loads the unscrambled segment limit from the segment descriptor specified with the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. The destination operand is a general-purpose register.
The processor performs access checks as part of the loading process. Once loaded in the destination register, soft-ware can compare the segment limit with the offset of a pointer.
The segment limit is a 20-bit value contained in bytes 0 and 1 and in the first 4 bits of byte 6 of the segment descriptor. If the descriptor has a byte granular segment limit (the granularity flag is set to 0), the destination operand is loaded with a byte granular value (byte limit). If the descriptor has a page granular segment limit (the granularity flag is set to 1), the LSL instruction will translate the page granular limit (page limit) into a byte limit before loading it into the destination operand. The translation is performed by shifting the 20-bit “raw” limit left 12 bits and filling the low-order 12 bits with 1s.
When the operand size is 32 bits, the 32-bit byte limit is stored in the destination operand. When the operand size is 16 bits, a valid 32-bit limit is computed; however, the upper 16 bits are truncated and only the low-order 16 bits are loaded into the destination operand.
This instruction performs the following checks before it loads the segment limit into the destination register:
If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no value is loaded in the destination operand.
| Type | Protected Mode | IA-32e Mode | ||
|---|---|---|---|---|
| Name | Valid | Name | Valid | |
|
0 1 2 3 4 5 6 7 8 9 A B C D E F |
Reserved Available 16-bit TSS LDT Busy 16-bit TSS 16-bit call gate 16-bit/32-bit task gate 16-bit interrupt gate 16-bit trap gate Reserved Available 32-bit TSS Reserved Busy 32-bit TSS 32-bit call gate Reserved 32-bit interrupt gate 32-bit trap gate |
No Yes Yes Yes No No No No No Yes No Yes No No No No |
Upper 8 byte of a 16-Byte descriptor Reserved LDT Reserved Reserved Reserved Reserved Reserved Reserved 64-bit TSS Reserved Busy 64-bit TSS 64-bit call gate Reserved 64-bit interrupt gate 64-bit trap gate |
Yes No Yes No No No No No No Yes No Yes No No No No |
IF SRC(Offset) > descriptor table limit
THEN ZF ← 0; FI;
Read segment descriptor;
IF SegmentDescriptor(Type) ≠ conforming code segment
and (CPL > DPL) OR (RPL > DPL)
or Segment type is not valid for instruction
THEN
ZF ← 0;
ELSE
temp ← SegmentLimit([SRC]);
IF (G ← 1)
THEN temp ← ShiftLeft(12, temp) OR 00000FFFH;
ELSE IF OperandSize = 32
THEN DEST ← temp; FI;
ELSE IF OperandSize = 64 (* REX.W used *)
THEN DEST (* Zero-extended *) ← temp; FI;
ELSE (* OperandSize = 16 *)
DEST ← temp AND FFFFH;
FI;
FI;
The ZF flag is set to 1 if the segment limit is loaded successfully; otherwise, it is set to 0.
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
| #UD | The LSL instruction cannot be executed in real-address mode. |
| #UD | The LSL instruction cannot be executed in virtual-8086 mode. |
Same exceptions as in protected mode.
| #SS(0) | If the memory operand effective address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory operand effective address is in a non-canonical form. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |