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PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation

Opcode/Instruction Op/En 64/32 bit Mode Support CPUID Feature Flag Description

0F DC /r1

PADDUSB mm, mm/m64

 RM V/V MMX Add packed unsigned byte integers from mm/m64 and mm and saturate the results.

66 0F DC /r

PADDUSB xmm1, xmm2/m128

 RM V/V SSE2 Add packed unsigned byte integers from xmm2/m128 and xmm1 saturate the results.

0F DD /r1

PADDUSW mm, mm/m64

 RM V/V MMX Add packed unsigned word integers from mm/m64 and mm and saturate the results.

66 0F DD /r

PADDUSW xmm1, xmm2/m128

 RM V/V SSE2 Add packed unsigned word integers from xmm2/m128 to xmm1 and saturate the results.

VEX.NDS.128.660F.WIG DC /r

VPADDUSB xmm1, xmm2, xmm3/m128

 RVM V/V AVX Add packed unsigned byte integers from xmm3/m128 to xmm2 and saturate the results.

VEX.NDS.128.66.0F.WIG DD /r

VPADDUSW xmm1, xmm2, xmm3/m128

 RVM V/V AVX Add packed unsigned word integers from xmm3/m128 to xmm2 and saturate the results.
VEX.NDS.256.66.0F.WIG DC /r VPADDUSB ymm1, ymm2, ymm3/m256 RVM V/V AVX2 Add packed unsigned byte integers from ymm2, and ymm3/m256 and store the saturated results in ymm1.
VEX.NDS.256.66.0F.WIG DD /r VPADDUSW ymm1, ymm2, ymm3/m256 RVM V/V AVX2 Add packed unsigned word integers from ymm2, and ymm3/m256 and store the saturated results in ymm1.

EVEX.NDS.128.66.0F.WIG DC /r

VPADDUSB xmm1 {k1}{z}, xmm2, xmm3/m128

 FVM V/V AVX512VL AVX512BW Add packed unsigned byte integers from xmm2, and xmm3/m128 and store the saturated results in xmm1 under writemask k1.

EVEX.NDS.256.66.0F.WIG DC /r

VPADDUSB ymm1 {k1}{z}, ymm2, ymm3/m256

 FVM V/V AVX512VL AVX512BW Add packed unsigned byte integers from ymm2, and ymm3/m256 and store the saturated results in ymm1 under writemask k1.

EVEX.NDS.512.66.0F.WIG DC /r

VPADDUSB zmm1 {k1}{z}, zmm2, zmm3/m512

 FVM V/V AVX512BW Add packed unsigned byte integers from zmm2, and zmm3/m512 and store the saturated results in zmm1 under writemask k1.

EVEX.NDS.128.66.0F.WIG DD /r

VPADDUSW xmm1 {k1}{z}, xmm2, xmm3/m128

 FVM V/V AVX512VL AVX512BW Add packed unsigned word integers from xmm2, and xmm3/m128 and store the saturated results in xmm1 under writemask k1.

EVEX.NDS.256.66.0F.WIG DD /r

VPADDUSW ymm1 {k1}{z}, ymm2, ymm3/m256

 FVM V/V AVX512VL AVX512BW Add packed unsigned word integers from ymm2, and ymm3/m256 and store the saturated results in ymm1 under writemask k1.

EVEX.NDS.512.66.0F.WIG DD /r

FVM

V/V

AVX512BW

Add packed unsigned word integers from zmm2, and zmm3/m512 and store the

VPADDUSW zmm1 {k1}{z}, zmm2, zmm3/m512

saturated results in zmm1 under writemask k1.

NOTES:

1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RM ModRM:reg (r, w) ModRM:r/m (r) NA NA
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA

Description

Performs a SIMD add of the packed unsigned integers from the source operand (second operand) and the destina-tion operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation. Overflow is handled with unsigned saturation, as described in the following paragraphs.

(V)PADDUSB performs a SIMD add of the packed unsigned integers with saturation from the first source operand and second source operand and stores the packed integer results in the destination operand. When an individual byte result is beyond the range of an unsigned byte integer (that is, greater than FFH), the saturated value of FFH is written to the destination operand.

(V)PADDUSW performs a SIMD add of the packed unsigned word integers with saturation from the first source operand and second source operand and stores the packed integer results in the destination operand. When an individual word result is beyond the range of an unsigned word integer (that is, greater than FFFFH), the saturated value of FFFFH is written to the destination operand.

EVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The second source operand is an ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination is an ZMM/YMM/XMM register.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding destination register destination are zeroed.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.

Operation


PADDUSB (with 64-bit operands)

DEST[7:0] ← SaturateToUnsignedByte(DEST[7:0] + SRC (7:0] );
(* Repeat add operation for 2nd through 7th bytes *)
DEST[63:56] ← SaturateToUnsignedByte(DEST[63:56] + SRC[63:56]


PADDUSB (with 128-bit operands)

DEST[7:0] ← SaturateToUnsignedByte (DEST[7:0] + SRC[7:0]);
(* Repeat add operation for 2nd through 14th bytes *)
DEST[127:120] ← SaturateToUnSignedByte (DEST[127:120] + SRC[127:120]);


VPADDUSB (VEX.128 encoded version)

DEST[7:0] (cid:197) SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] (cid:197) SaturateToUnsignedByte (SRC1[111:120] + SRC2[127:120]);
DEST[VLMAX-1:128] (cid:197) 0


VPADDUSB (VEX.256 encoded version)

DEST[7:0] (cid:197) SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);
(* Repeat add operation for 2nd through 31st bytes *)
DEST[255:248](cid:197) SaturateToUnsignedByte (SRC1[255:248] + SRC2[255:248]);


PADDUSW (with 64-bit operands)

DEST[15:0] ← SaturateToUnsignedWord(DEST[15:0] + SRC[15:0] );
(* Repeat add operation for 2nd and 3rd words *)
DEST[63:48] ← SaturateToUnsignedWord(DEST[63:48] + SRC[63:48] );


PADDUSW (with 128-bit operands)

DEST[15:0] ← SaturateToUnsignedWord (DEST[15:0] + SRC[15:0]);
(* Repeat add operation for 2nd through 7th words *)
DEST[127:112] ← SaturateToUnSignedWord (DEST[127:112] + SRC[127:112]);


VPADDUSW (VEX.128 encoded version)

DEST[15:0] (cid:197) SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] (cid:197) SaturateToUnsignedWord (SRC1[127:112] + SRC2[127:112]);
DEST[VLMAX-1:128] (cid:197) 0


VPADDUSW (VEX.256 encoded version)

DEST[15:0] (cid:197) SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);
(* Repeat add operation for 2nd through 15th words *)
DEST[255:240] (cid:197) SaturateToUnsignedWord (SRC1[255:240] + SRC2[255:240])
VPADDUSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 8
    IF k1[j] OR *no writemask*
        THEN DEST[i+7:i] (cid:197) SaturateToUnsignedByte (SRC1[i+7:i] + SRC2[i+7:i])
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[i+7:i] remains unchanged*
            ELSE *zeroing-masking*
            ; zeroing-masking
            DEST[i+7:i] = 0
        FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0


VPADDUSW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 16
    IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] (cid:197) SaturateToUnsignedWord (SRC1[i+15:i] + SRC2[i+15:i])
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[i+15:i] remains unchanged*
            ELSE *zeroing-masking*
            ; zeroing-masking
            DEST[i+15:i] = 0
        FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0



Intel C/C++ Compiler Intrinsic Equivalent


PADDUSB:
__m64 _mm_adds_pu8(__m64 m1, __m64 m2)
PADDUSW:
__m64 _mm_adds_pu16(__m64 m1, __m64 m2)
(V)PADDUSB:
__m128i _mm_adds_epu8 ( __m128i a, __m128i b)
(V)PADDUSW:
__m128i _mm_adds_epu16 ( __m128i a, __m128i b)
VPADDUSB:
__m256i _mm256_adds_epu8 ( __m256i a, __m256i b)
VPADDUSW:

__m256i _mm256_adds_epu16 ( __m256i a, __m256i b)
VPADDUSB__m512i _mm512_adds_epu8 ( __m512i a, __m512i b)
VPADDUSW__m512i _mm512_adds_epu16 ( __m512i a, __m512i b)
VPADDUSB__m512i _mm512_mask_adds_epu8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)
VPADDUSW__m512i _mm512_mask_adds_epu16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)
VPADDUSB__m512i _mm512_maskz_adds_epu8 (__mmask64 m, __m512i a, __m512i b)
VPADDUSW__m512i _mm512_maskz_adds_epu16 (__mmask32 m, __m512i a, __m512i b)
VPADDUSB__m256i _mm256_mask_adds_epu8 (__m256i s, __mmask32 m, __m256i a, __m256i b)
VPADDUSW__m256i _mm256_mask_adds_epu16 (__m256i s, __mmask16 m, __m256i a, __m256i b)
VPADDUSB__m256i _mm256_maskz_adds_epu8 (__mmask32 m, __m256i a, __m256i b)
VPADDUSW__m256i _mm256_maskz_adds_epu16 (__mmask16 m, __m256i a, __m256i b)
VPADDUSB__m128i _mm_mask_adds_epu8 (__m128i s, __mmask16 m, __m128i a, __m128i b)
VPADDUSW__m128i _mm_mask_adds_epu16 (__m128i s, __mmask8 m, __m128i a, __m128i b)
VPADDUSB__m128i _mm_maskz_adds_epu8 (__mmask16 m, __m128i a, __m128i b)
VPADDUSW__m128i _mm_maskz_adds_epu16 (__mmask8 m, __m128i a, __m128i b)




Flags Affected


None.


Numeric Exceptions


None.


Other Exceptions


Non-EVEX-encoded instruction, see Exceptions Type 4.


EVEX-encoded instruction, see Exceptions Type E4.nb.