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PCMPEQQ — Compare Packed Qword Data for Equal

Opcode/Instruction Op/En 64/32 bit Mode Support CPUID Feature Flag Description
66 0F 38 29 /r PCMPEQQ xmm1, xmm2/m128 RM V/V SSE4_1 Compare packed qwords in xmm2/m128 and xmm1 for equality.
VEX.NDS.128.66.0F38.WIG 29 /r VPCMPEQQ xmm1, xmm2, xmm3/m128 RVM V/V AVX Compare packed quadwords in xmm3/m128 and xmm2 for equality.
VEX.NDS.256.66.0F38.WIG 29 /r VPCMPEQQ ymm1, ymm2, ymm3 /m256 RVM V/V AVX2 Compare packed quadwords in ymm3/m256 and ymm2 for equality.

EVEX.NDS.128.66.0F38.W1 29 /r

VPCMPEQQ k1 {k2}, xmm2, xmm3/m128/m64bcst

 FV V/V

AVX512VL

AVX512F

 Compare Equal between int64 vector xmm2 and int64 vector xmm3/m128/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.

EVEX.NDS.256.66.0F38.W1 29 /r

VPCMPEQQ k1 {k2}, ymm2, ymm3/m256/m64bcst

 FV V/V

AVX512VL

AVX512F

 Compare Equal between int64 vector ymm2 and int64 vector ymm3/m256/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.

EVEX.NDS.512.66.0F38.W1 29 /r

VPCMPEQQ k1 {k2}, zmm2, zmm3/m512/m64bcst

 FV V/V AVX512F Compare Equal between int64 vector zmm2 and int64 vector zmm3/m512/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RM ModRM:reg (r, w) ModRM:r/m (r) NA NA
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA

Description

Performs an SIMD compare for equality of the packed quadwords in the destination operand (first operand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data element in the desti-nation is set to all 1s; otherwise, it is set to 0s.

128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.

EVEX encoded VPCMPEQQ: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.

Operation


PCMPEQQ (with 128-bit operands)

IF (DEST[63:0] = SRC[63:0])
    THEN DEST[63:0] (cid:197) FFFFFFFFFFFFFFFFH;
    ELSE DEST[63:0] (cid:197) 0; FI;
IF (DEST[127:64] = SRC[127:64])
    THEN DEST[127:64] (cid:197) FFFFFFFFFFFFFFFFH;
    ELSE DEST[127:64] (cid:197) 0; FI;
DEST[MAX_VL-1:128] (Unmodified)


COMPARE_QWORDS_EQUAL (SRC1, SRC2)

IF SRC1[63:0] = SRC2[63:0]
    THEN DEST[63:0] (cid:197)FFFFFFFFFFFFFFFFH;
    ELSE DEST[63:0] (cid:197)0; FI;
IF SRC1[127:64] = SRC2[127:64]
    THEN DEST[127:64] (cid:197)FFFFFFFFFFFFFFFFH;
    ELSE DEST[127:64] (cid:197)0; FI;


VPCMPEQQ (VEX.128 encoded version)

DEST[127:0] (cid:197)COMPARE_QWORDS_EQUAL(SRC1,SRC2)
DEST[VLMAX-1:128] (cid:197) 0


VPCMPEQQ (VEX.256 encoded version)

DEST[127:0] (cid:197)COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] (cid:197)COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] (cid:197) 0


VPCMPEQQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k2[j] OR *no writemask*
        THEN
        IF (EVEX.b = 1) AND (SRC2 *is memory*)
            THEN CMP (cid:197) SRC1[i+63:i] = SRC2[63:0];
            ELSE CMP (cid:197) SRC1[i+63:i] = SRC2[i+63:i];
        FI;
        IF CMP = TRUE
            THEN DEST[j] (cid:197) 1;
            ELSE DEST[j] (cid:197) 0; FI;
        ELSE
        DEST[j] (cid:197) 0
        ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] (cid:197) 0



Intel C/C++ Compiler Intrinsic Equivalent



VPCMPEQQ __mmask8 _mm512_cmpeq_epi64_mask( __m512i a, __m512i b);
VPCMPEQQ __mmask8 _mm512_mask_cmpeq_epi64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPEQQ __mmask8 _mm256_cmpeq_epi64_mask( __m256i a, __m256i b);
VPCMPEQQ __mmask8 _mm256_mask_cmpeq_epi64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPEQQ __mmask8 _mm_cmpeq_epi64_mask( __m128i a, __m128i b);
VPCMPEQQ __mmask8 _mm_mask_cmpeq_epi64_mask(__mmask8 k, __m128i a, __m128i b);

(V)PCMPEQQ:
__m128i _mm_cmpeq_epi64(__m128i a, __m128i b);
VPCMPEQQ:
__m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);



Flags Affected


None.


SIMD Floating-Point Exceptions


None.


Other Exceptions


Non-EVEX-encoded instruction, see Exceptions Type 4.


EVEX-encoded VPCMPEQQ, see Exceptions Type E4.