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PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result

Opcode/Instruction Op/En 64/32 bit Mode Support CPUID Feature Flag Description

66 0F 38 40 /r

PMULLD xmm1, xmm2/m128

 RM V/V SSE4_1 Multiply the packed dword signed integers in xmm1 and xmm2/m128 and store the low 32 bits of each product in xmm1.

VEX.NDS.128.66.0F38.WIG 40 /r

VPMULLD xmm1, xmm2, xmm3/m128

 RVM V/V AVX Multiply the packed dword signed integers in xmm2 and xmm3/m128 and store the low 32 bits of each product in xmm1.

VEX.NDS.256.66.0F38.WIG 40 /r

VPMULLD ymm1, ymm2, ymm3/m256

 RVM V/V AVX2 Multiply the packed dword signed integers in ymm2 and ymm3/m256 and store the low 32 bits of each product in ymm1.

EVEX.NDS.128.66.0F38.W0 40 /r

VPMULLD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst

 FV V/V AVX512VL AVX512F Multiply the packed dword signed integers in xmm2 and xmm3/m128/m32bcst and store the low 32 bits of each product in xmm1 under writemask k1.

EVEX.NDS.256.66.0F38.W0 40 /r

VPMULLD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst

 FV V/V AVX512VL AVX512F Multiply the packed dword signed integers in ymm2 and ymm3/m256/m32bcst and store the low 32 bits of each product in ymm1 under writemask k1.

EVEX.NDS.512.66.0F38.W0 40 /r

VPMULLD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst

 FV V/V AVX512F Multiply the packed dword signed integers in zmm2 and zmm3/m512/m32bcst and store the low 32 bits of each product in zmm1 under writemask k1.

EVEX.NDS.128.66.0F38.W1 40 /r

VPMULLQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst

 FV V/V AVX512VL AVX512DQ Multiply the packed qword signed integers in xmm2 and xmm3/m128/m64bcst and store the low 64 bits of each product in xmm1 under writemask k1.

EVEX.NDS.256.66.0F38.W1 40 /r

VPMULLQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst

 FV V/V AVX512VL AVX512DQ Multiply the packed qword signed integers in ymm2 and ymm3/m256/m64bcst and store the low 64 bits of each product in ymm1 under writemask k1.

EVEX.NDS.512.66.0F38.W1 40 /r

VPMULLQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst

 FV V/V AVX512DQ Multiply the packed qword signed integers in zmm2 and zmm3/m512/m64bcst and store the low 64 bits of each product in zmm1 under writemask k1.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RM ModRM:reg (r, w) ModRM:r/m (r) NA NA
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA

Description

Performs a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source operand with the corresponding element in the second source operand. The low 32/64 bits of each 64/128-bit intermediate results are stored to the destination operand.

128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM destina-tion register remain unchanged.

VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.

VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register or 256-bit memory location. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.

Operation


VPMULLQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k1[j] OR *no writemask* THEN
        IF (EVEX.b == 1) AND (SRC2 *is memory*)
            THEN Temp[127:0] (cid:197) SRC1[i+63:i] * SRC2[63:0]
            ELSE Temp[127:0] (cid:197) SRC1[i+63:i] * SRC2[i+63:i]
        FI;
        DEST[i+63:i] (cid:197) Temp[63:0]
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[i+63:i] remains unchanged*
            ELSE
            ; zeroing-masking
            DEST[i+63:i] (cid:197) 0
        FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0


VPMULLD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask* THEN
        IF (EVEX.b = 1) AND (SRC2 *is memory*)
            THEN Temp[63:0] (cid:197) SRC1[i+31:i] * SRC2[31:0]
            ELSE Temp[63:0] (cid:197) SRC1[i+31:i] * SRC2[i+31:i]
        FI;
        DEST[i+31:i] (cid:197) Temp[31:0]
        ELSE
        IF *merging-masking*
            ; merging-masking
            *DEST[i+31:i] remains unchanged*
            ELSE
            ; zeroing-masking
            DEST[i+31:i] (cid:197) 0
        FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0


VPMULLD (VEX.256 encoded version)

Temp0[63:0] (cid:197) SRC1[31:0] * SRC2[31:0]
Temp1[63:0] (cid:197) SRC1[63:32] * SRC2[63:32]
Temp2[63:0] (cid:197) SRC1[95:64] * SRC2[95:64]
Temp3[63:0] (cid:197) SRC1[127:96] * SRC2[127:96]
Temp4[63:0] (cid:197) SRC1[159:128] * SRC2[159:128]
Temp5[63:0] (cid:197) SRC1[191:160] * SRC2[191:160]
Temp6[63:0] (cid:197) SRC1[223:192] * SRC2[223:192]
Temp7[63:0] (cid:197) SRC1[255:224] * SRC2[255:224]
DEST[31:0] (cid:197) Temp0[31:0]
DEST[63:32] (cid:197) Temp1[31:0]
DEST[95:64] (cid:197) Temp2[31:0]
DEST[127:96] (cid:197) Temp3[31:0]
DEST[159:128] (cid:197) Temp4[31:0]
DEST[191:160] (cid:197) Temp5[31:0]
DEST[223:192] (cid:197) Temp6[31:0]
DEST[255:224] (cid:197) Temp7[31:0]
DEST[MAX_VL-1:256] (cid:197) 0


VPMULLD (VEX.128 encoded version)

Temp0[63:0] (cid:197) SRC1[31:0] * SRC2[31:0]
Temp1[63:0] (cid:197) SRC1[63:32] * SRC2[63:32]
Temp2[63:0] (cid:197) SRC1[95:64] * SRC2[95:64]
Temp3[63:0] (cid:197) SRC1[127:96] * SRC2[127:96]
DEST[31:0] (cid:197) Temp0[31:0]
DEST[63:32] (cid:197) Temp1[31:0]
DEST[95:64] (cid:197) Temp2[31:0]
DEST[127:96] (cid:197) Temp3[31:0]
DEST[MAX_VL-1:128] (cid:197) 0
PMULLD (128-bit Legacy SSE version)
Temp0[63:0] (cid:197) DEST[31:0] * SRC[31:0]
Temp1[63:0] (cid:197) DEST[63:32] * SRC[63:32]
Temp2[63:0] (cid:197) DEST[95:64] * SRC[95:64]
Temp3[63:0] (cid:197) DEST[127:96] * SRC[127:96]
DEST[31:0] (cid:197) Temp0[31:0]
DEST[63:32] (cid:197) Temp1[31:0]
DEST[95:64] (cid:197) Temp2[31:0]
DEST[127:96] (cid:197) Temp3[31:0]
DEST[MAX_VL-1:128] (Unmodified)



Intel C/C++ Compiler Intrinsic Equivalent


VPMULLD __m512i _mm512_mullo_epi32(__m512i a, __m512i b);
VPMULLD __m512i _mm512_mask_mullo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMULLD __m512i _mm512_maskz_mullo_epi32( __mmask16 k, __m512i a, __m512i b);
VPMULLD __m256i _mm256_mask_mullo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULLD __m256i _mm256_maskz_mullo_epi32( __mmask8 k, __m256i a, __m256i b);
VPMULLD __m128i _mm_mask_mullo_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLD __m128i _mm_maskz_mullo_epi32( __mmask8 k, __m128i a, __m128i b);
VPMULLD __m256i _mm256_mullo_epi32(__m256i a, __m256i b);
PMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b);
VPMULLQ __m512i _mm512_mullo_epi64(__m512i a, __m512i b);
VPMULLQ __m512i _mm512_mask_mullo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMULLQ __m512i _mm512_maskz_mullo_epi64( __mmask8 k, __m512i a, __m512i b);
VPMULLQ __m256i _mm256_mullo_epi64(__m256i a, __m256i b);
VPMULLQ __m256i _mm256_mask_mullo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULLQ __m256i _mm256_maskz_mullo_epi64( __mmask8 k, __m256i a, __m256i b);
VPMULLQ __m128i _mm_mullo_epi64(__m128i a, __m128i b);
VPMULLQ __m128i _mm_mask_mullo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLQ __m128i _mm_maskz_mullo_epi64( __mmask8 k, __m128i a, __m128i b);



SIMD Floating-Point Exceptions


None


Other Exceptions


Non-EVEX-encoded instruction, see Exceptions Type 4.


EVEX-encoded instruction, see Exceptions Type E4.