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SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value

Opcode/Instruction Op /En 64/32 bit Mode Support CPUID Feature Flag Description

F2 0F 51/r

SQRTSD xmm1,xmm2/m64

 RM V/V SSE2 Computes square root of the low double-precision floating-point value in xmm2/m64 and stores the results in xmm1.

VEX.NDS.128.F2.0F.WIG 51/r

VSQRTSD xmm1,xmm2, xmm3/m64

 RVM V/V AVX Computes square root of the low double-precision floating-point value in xmm3/m64 and stores the results in xmm1. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64].

EVEX.NDS.LIG.F2.0F.W1 51/r

VSQRTSD xmm1 {k1}{z}, xmm2, xmm3/m64{er}

 T1S V/V AVX512F Computes square root of the low double-precision floating-point value in xmm3/m64 and stores the results in xmm1 under writemask k1. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64].

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RM ModRM:reg (w) ModRM:r/m (r) NA NA
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA

Description

Computes the square root of the low double-precision floating-point value in the second source operand and stores the double-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM registers.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. The quadword at bits 127:64 of the destination operand remains unchanged. Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged.

VEX.128 and EVEX encoded versions: Bits 127:64 of the destination operand are copied from the corresponding bits of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.

EVEX encoded version: The low quadword element of the destination operand is updated according to the writemask.

Software should ensure VSQRTSD is encoded with VEX.L=0. Encoding VSQRTSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.

Operation


VSQRTSD (EVEX encoded version)

IF (EVEX.b = 1) AND (SRC2 *is register*)
    THEN
    SET_RM(EVEX.RC);
    ELSE
    SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN
    DEST[63:0] (cid:197) SQRT(SRC2[63:0])
    ELSE
    IF *merging-masking*
        ; merging-masking
        THEN *DEST[63:0] remains unchanged*
        ELSE
        ; zeroing-masking
        THEN DEST[63:0] (cid:197) 0
    FI;
FI;
DEST[127:64] (cid:197) SRC1[127:64]
DEST[MAX_VL-1:128] (cid:197) 0


VSQRTSD (VEX.128 encoded version)

DEST[63:0] (cid:197)SQRT(SRC2[63:0])
DEST[127:64] (cid:197)SRC1[127:64]
DEST[MAX_VL-1:128] (cid:197)0


SQRTSD (128-bit Legacy SSE version)

DEST[63:0] (cid:197)SQRT(SRC[63:0])
DEST[MAX_VL-1:64] (Unmodified)



Intel C/C++ Compiler Intrinsic Equivalent


VSQRTSD __m128d _mm_sqrt_round_sd(__m128d a, __m128d b, int r);
VSQRTSD __m128d _mm_mask_sqrt_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int r);
VSQRTSD __m128d _mm_maskz_sqrt_round_sd(__mmask8 k, __m128d a, __m128d b, int r);
SQRTSD __m128d _mm_sqrt_sd (__m128d a, __m128d b)



SIMD Floating-Point Exceptions


Invalid, Precision, Denormal


Other Exceptions


Non-EVEX-encoded instruction, see Exceptions Type 3.


EVEX-encoded instruction, see Exceptions Type E3.