VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single-Precision Floating-Point Values

Instruction Operand Encoding

Description

Performs a SIMD multiply-add computation on single-precision floating-point values using three source operands and writes the multiply-add results in the destination operand. The destination operand is also the first source operand. The first and second operands are XMM registers. The third source operand can be a XMM register or a 32-bit memory location.

VFMADD132SS: Multiplies the low single-precision floating-point value from the first source operand to the low single-precision floating-point value in the third source operand, adds the infinite precision intermediate result to the low single-precision floating-point value in the second source operand, performs rounding and stores the resulting single-precision floating-point value to the destination operand (first source operand).

VFMADD213SS: Multiplies the low single-precision floating-point value from the second source operand to the low single-precision floating-point value in the first source operand, adds the infinite precision intermediate result to the low single-precision floating-point value in the third source operand, performs rounding and stores the resulting single-precision floating-point value to the destination operand (first source operand).

VFMADD231SS: Multiplies the low single-precision floating-point value from the second source operand to the low single-precision floating-point value in the third source operand, adds the infinite precision intermediate result to the low single-precision floating-point value in the first source operand, performs rounding and stores the resulting single-precision floating-point value to the destination operand (first source operand).

VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.

EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.

Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

Operation

In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
    SET_RM(EVEX.RC);
    ELSE
    SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN
    DEST[31:0] (cid:197) RoundFPControl(DEST[31:0]*SRC3[31:0] + SRC2[31:0])
    ELSE
    IF *merging-masking*
        ; merging-masking
        THEN *DEST[31:0] remains unchanged*
        ELSE
        ; zeroing-masking
        THEN DEST[31:0] (cid:197) 0
    FI;
FI;
DEST[127:32] (cid:197) DEST[127:32]
DEST[MAX_VL-1:128] (cid:197) 0

IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
    SET_RM(EVEX.RC);
    ELSE
    SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN
    DEST[31:0] (cid:197) RoundFPControl(SRC2[31:0]*DEST[31:0] + SRC3[31:0])
    ELSE
    IF *merging-masking*
        ; merging-masking
        THEN *DEST[31:0] remains unchanged*
        ELSE
        ; zeroing-masking
        THEN DEST[31:0] (cid:197) 0
    FI;
FI;
DEST[127:32] (cid:197) DEST[127:32]
DEST[MAX_VL-1:128] (cid:197) 0

IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
    SET_RM(EVEX.RC);
    ELSE
    SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN
    DEST[31:0] (cid:197) RoundFPControl(SRC2[31:0]*SRC3[31:0] + DEST[31:0])
    ELSE
    IF *merging-masking*
        ; merging-masking
        THEN *DEST[31:0]] remains unchanged*
        ELSE
        ; zeroing-masking
        THEN DEST[31:0] (cid:197) 0
    FI;
FI;
DEST[127:32] (cid:197) DEST[127:32]
DEST[MAX_VL-1:128] (cid:197) 0

DEST[31:0] (cid:197)RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] + SRC2[31:0])
DEST[127:32] (cid:197)DEST[127:32]
DEST[MAX_VL-1:128] (cid:197)0

DEST[31:0] (cid:197)RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] + SRC3[31:0])
DEST[127:32] (cid:197)DEST[127:32]
DEST[MAX_VL-1:128] (cid:197)0

DEST[31:0] (cid:197)RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] + DEST[31:0])
DEST[127:32] (cid:197)DEST[127:32]
DEST[MAX_VL-1:128] (cid:197)0

Intel C/C++ Compiler Intrinsic Equivalent

VFMADDxxxSS __m128 _mm_fmadd_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_mask_fmadd_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMADDxxxSS __m128 _mm_maskz_fmadd_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMADDxxxSS __m128 _mm_mask3_fmadd_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMADDxxxSS __m128 _mm_mask_fmadd_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_maskz_fmadd_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_mask3_fmadd_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFMADDxxxSS __m128 _mm_fmadd_ss (__m128 a, __m128 b, __m128 c);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions