VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values

Instruction Operand Encoding

Description

Extracts the biased exponents from the normalized SP FP representation of each dword element of the source operand (the second operand) as unbiased signed integer value, or convert the denormal representation of input data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to single-preci-sion FP value and written to the corresponding dword elements of the destination operand (the first operand) as SP FP numbers.

The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location.

EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-sentation). Special cases of input values are listed in Table 5-8.

The formula is:

GETEXP(x) = floor(log₂(|x|))

Notation floor(x) stands for maximal integer not exceeding real number x.

Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD FP exceptions.

Table 5-8. VGETEXPPS/SS Special Cases

Operation

NormalizeExpTinySPFP(SRC[31:0])
{
// Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.
Src.Jbit (cid:197) 0;
Dst.exp (cid:197) 1;
Dst.fraction (cid:197) SRC[22:0];
WHILE(Src.Jbit = 0)
{
Src.Jbit (cid:197) Dst.fraction[22];
// Get the fraction MSB
Dst.fraction (cid:197) Dst.fraction << 1 ;
// One bit shift left
Dst.exp-- ;
// Decrement the exponent
}
Dst.fraction (cid:197) 0;
// zero out fraction bits
Dst.sign (cid:197) 1;
// Return negative sign
TMP[31:0] (cid:197) MXCSR.DAZ? 0 : (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction) ;
Return (TMP[31:0]);
}
ConvertExpSPFP(SRC[31:0])
{
Src.sign (cid:197) 0;
// Zero out sign bit
Src.exp (cid:197) SRC[30:23];
Src.fraction (cid:197) SRC[22:0];
// Check for NaN
IF (SRC = NaN)
    {
    IF ( SRC = SNAN ) SET IE;
        Return QNAN(SRC);
        }
        // Check for +INF
        IF (SRC = +INF) Return (SRC);
            // check if zero operand
            IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
                }
                ELSE
                // check if denormal operand (notice that MXCSR.DAZ = 0)
                {
                IF ((Src.exp = 0) AND (Src.fraction != 0))
                    {
                    TMP[31:0] (cid:197) NormalizeExpTinySPFP(SRC[31:0]) ;
                    // Get Normalized Exponent
                    Set #DE
                    }
                    ELSE
                    // exponent value is correct
                    {
                    Dst.fraction (cid:197) 0;
                    // zero out fraction bits
                    TMP[31:0] (cid:197) (Src.sign << 31) OR (Src.exp << 23) OR (Src.fraction) ;
                    }
                    TMP (cid:197) SAR(TMP, 23) ;
                    // Shift Arithmetic Right
                    TMP (cid:197) TMP – 127;
                    // Subtract Bias
                    Return CvtI2D(TMP) ;
                    // Convert INT to Single-Precision FP number
                    }
                    }

(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask*
        THEN
        IF (EVEX.b = 1) AND (SRC *is memory*)
            THEN
            DEST[i+31:i] (cid:197)
            ConvertExpSPFP(SRC[31:0])
            ELSE
            DEST[i+31:i] (cid:197)
            ConvertExpSPFP(SRC[i+31:i])
        FI;
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[i+31:i] remains unchanged*
            ELSE
            ; zeroing-masking
            DEST[i+31:i] (cid:197) 0
        FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0

Intel C/C++ Compiler Intrinsic Equivalent

VGETEXPPS __m512 _mm512_getexp_ps( __m512 a);
VGETEXPPS __m512 _mm512_mask_getexp_ps(__m512 s, __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_maskz_getexp_ps( __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_getexp_round_ps( __m512 a, int sae);
VGETEXPPS __m512 _mm512_mask_getexp_round_ps(__m512 s, __mmask16 k, __m512 a, int sae);
VGETEXPPS __m512 _mm512_maskz_getexp_round_ps( __mmask16 k, __m512 a, int sae);
VGETEXPPS __m256 _mm256_getexp_ps(__m256 a);
VGETEXPPS __m256 _mm256_mask_getexp_ps(__m256 s, __mmask8 k, __m256 a);
VGETEXPPS __m256 _mm256_maskz_getexp_ps( __mmask8 k, __m256 a);
VGETEXPPS __m128 _mm_getexp_ps(__m128 a);
VGETEXPPS __m128 _mm_mask_getexp_ps(__m128 s, __mmask8 k, __m128 a);
VGETEXPPS __m128 _mm_maskz_getexp_ps( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions

See Exceptions Type E2.