VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic

Instruction Operand Encoding

Description

Shifts the bits in the individual data elements (word/doublewords/quadword) in the first source operand (the second operand) to the right by the number of bits specified in the count value of respective data elements in the second source operand (the third operand). As the bits in the data elements are shifted right, the empty high-order bits are set to the MSB (sign extension).

The count values are specified individually in each data element of the second source operand. If the unsigned integer value specified in the respective data element of the second source operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination data element are filled with the corresponding sign bit of the source element.

The count values are specified individually in each data element of the second source operand. If the unsigned integer value specified in the respective data element of the second source operand is greater than 16 (for word), 31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.

VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be either an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.

VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be either an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.

EVEX.512/256/128 encoded VPSRAVD/W: The destination and first source operands are ZMM/YMM/XMM registers. The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.

EVEX.512/256/128 encoded VPSRAVQ: The destination and first source operands are ZMM/YMM/XMM registers. The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is conditionally updated with writemask k1.

Operation

(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 16
    IF k1[j] OR *no writemask*
        THEN
        COUNT (cid:197) SRC2[i+3:i]
        IF COUNT < 16
            THEN
            DEST[i+15:i] (cid:197) SignExtend(SRC1[i+15:i] >> COUNT)
            ELSE
            FOR k(cid:197) 0 TO 15
                DEST[i+k] (cid:197) SRC1[i+15]
            ENDFOR;
        FI
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[i+15:i] remains unchanged*
            ELSE
            ; zeroing-masking
            DEST[i+15:i] (cid:197) 0
        FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0;

COUNT_0 (cid:197) SRC2[31 : 0]
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 (cid:197) SRC2[100 : 96];
DEST[31:0] (cid:197) SignExtend(SRC1[31:0] >> COUNT_0);
(* Repeat shift operation for 2nd through 4th dwords *)
DEST[127:96] (cid:197) SignExtend(SRC1[127:96] >> COUNT_3);
DEST[MAX_VL-1:128] (cid:197) 0;

COUNT_0 (cid:197) SRC2[31 : 0];
(* Repeat Each COUNT_i for the 2nd through 8th dwords of SRC2*)
COUNT_7 (cid:197) SRC2[228 : 224];
DEST[31:0] (cid:197) SignExtend(SRC1[31:0] >> COUNT_0);
(* Repeat shift operation for 2nd through 7th dwords *)
DEST[255:224] (cid:197) SignExtend(SRC1[255:224] >> COUNT_7);
DEST[MAX_VL-1:256] (cid:197) 0;

(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask* THEN
        IF (EVEX.b = 1) AND (SRC2 *is memory*)
            THEN
            COUNT (cid:197) SRC2[4:0]
            IF COUNT < 32
                THEN
                DEST[i+31:i] (cid:197) SignExtend(SRC1[i+31:i] >> COUNT)
                ELSE
                FOR k(cid:197) 0 TO 31
                    DEST[i+k] (cid:197) SRC1[i+31]
                ENDFOR;
            FI
            ELSE
            COUNT (cid:197) SRC2[i+4:i]
            IF COUNT < 32
                THEN
                DEST[i+31:i] (cid:197) SignExtend(SRC1[i+31:i] >> COUNT)
                ELSE
                FOR k(cid:197) 0 TO 31
                    DEST[i+k] (cid:197) SRC1[i+31]
                ENDFOR;
            FI
        FI;
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[31:0] remains unchanged*
            ELSE
            ; zeroing-masking
            DEST[31:0] (cid:197) 0
        FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0;

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k1[j] OR *no writemask* THEN
        IF (EVEX.b = 1) AND (SRC2 *is memory*)
            THEN
            COUNT (cid:197) SRC2[5:0]
            IF COUNT < 64
                THEN
                DEST[i+63:i] (cid:197) SignExtend(SRC1[i+63:i] >> COUNT)
                ELSE
                FOR k(cid:197) 0 TO 63
                    DEST[i+k] (cid:197) SRC1[i+63]
                ENDFOR;
            FI
            ELSE
            COUNT (cid:197) SRC2[i+5:i]
            IF COUNT < 64
                THEN
                DEST[i+63:i] (cid:197) SignExtend(SRC1[i+63:i] >> COUNT)
                ELSE
                FOR k(cid:197) 0 TO 63
                    DEST[i+k] (cid:197) SRC1[i+63]
                ENDFOR;
            FI
        FI;
        ELSE
        IF *merging-masking*
            ; merging-masking
            THEN *DEST[63:0] remains unchanged*
            ELSE
            ; zeroing-masking
            DEST[63:0] (cid:197) 0
        FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0;

Intel C/C++ Compiler Intrinsic Equivalent

VPSRAVD __m512i _mm512_srav_epi32(__m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_mask_srav_epi32(__m512i s, __mmask16 m, __m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_maskz_srav_epi32(__mmask16 m, __m512i a, __m512i cnt);
VPSRAVD __m256i _mm256_srav_epi32(__m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_mask_srav_epi32(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_maskz_srav_epi32(__mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m128i _mm_srav_epi32(__m128i a, __m128i cnt);
VPSRAVD __m128i _mm_mask_srav_epi32(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVD __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m512i _mm512_srav_epi64(__m512i a, __m512i cnt);
VPSRAVQ __m512i _mm512_mask_srav_epi64(__m512i s, __mmask8 m, __m512i a, __m512i cnt);
VPSRAVQ __m512i _mm512_maskz_srav_epi64( __mmask8 m, __m512i a, __m512i cnt);
VPSRAVQ __m256i _mm256_srav_epi64(__m256i a, __m256i cnt);
VPSRAVQ __m256i _mm256_mask_srav_epi64(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVQ __m256i _mm256_maskz_srav_epi64( __mmask8 m, __m256i a, __m256i cnt);
VPSRAVQ __m128i _mm_srav_epi64(__m128i a, __m128i cnt);
VPSRAVQ __m128i _mm_mask_srav_epi64(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m128i _mm_maskz_srav_epi64( __mmask8 m, __m128i a, __m128i cnt);
VPSRAVW __m512i _mm512_srav_epi16(__m512i a, __m512i cnt);
VPSRAVW __m512i _mm512_mask_srav_epi16(__m512i s, __mmask32 m, __m512i a, __m512i cnt);
VPSRAVW __m512i _mm512_maskz_srav_epi16(__mmask32 m, __m512i a, __m512i cnt);
VPSRAVW __m256i _mm256_srav_epi16(__m256i a, __m256i cnt);
VPSRAVW __m256i _mm256_mask_srav_epi16(__m256i s, __mmask16 m, __m256i a, __m256i cnt);
VPSRAVW __m256i _mm256_maskz_srav_epi16(__mmask16 m, __m256i a, __m256i cnt);
VPSRAVW __m128i _mm_srav_epi16(__m128i a, __m128i cnt);
VPSRAVW __m128i _mm_mask_srav_epi16(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVW __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);
VPSRAVD __m256i _mm256_srav_epi32 (__m256i m, __m256i count)

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Exceptions Type 4.

EVEX-encoded instruction, see Exceptions Type E4.