ARMv8-A A64 Instruction Set Reference
An independent, comprehensive reference for the AArch64 (A64) instruction set as used when reversing ARM64 binaries, firmware, kernels or shellcode on Linux, Android, macOS/iOS and Windows: base integer, bitfield, branches, loads and stores, the LSE atomics, system instructions, pointer authentication, memory tagging, CRC and the full cryptography set, scalar floating point and the complete Advanced SIMD (NEON) catalogue — three-same, three-different, two-register misc, across-lanes, by-element, shifts, permutes, table lookup and structure loads/stores. Every encoding below is checked against the LLVM assembler. The Scalable Vector Extension (SVE/SVE2) is not covered.
- Registers
- Condition codes
- Encoding groups
- Bitmask immediates
- Extend & shift
- System registers
- Aliases
- Instructions
- Calling convention
Registers
General purpose
X0–X30: 64-bit registers;W0–W30are their low 32 bits (writing W zeroes the top 32).X30= LR (link register),X29= FP (frame pointer).X16/X17= IP0/IP1 (veneers, PLT;X16= syscall nr on macOS).X18= platform register (reserved on Apple/Windows).X8= indirect result / Linux syscall number.
Encoding 31
- Register number 31 means XZR/WZR (the zero register) for most instructions: reads as 0, writes discarded.
- In a few instructions (
addwith sp, memory addressing) it means SP instead. PCis not a general register; it is read withadr/adrp, written by branches.
SIMD / FP
V0–V31: 128-bit vector registers.- Scalar views:
Bn(8),Hn(16),Sn(32),Dn(64),Qn(128) — the same register file. - Vector views:
Vn.8B/16B,.4H/8H,.2S/4S,.1D/2D. - Only
D8–D15(low 64 bits) are callee-saved.
State & exception levels
- PSTATE condition flags: N (negative), Z (zero), C (carry), V (overflow).
- EL0 user, EL1 kernel, EL2 hypervisor, EL3 secure monitor.
- Each level above EL0 has its own
SP_ELx,ELR_ELx,SPSR_ELx.
Condition codes (the 4-bit cond field)
| cond | Mnemonic | Flags tested | Meaning |
|---|---|---|---|
| 0000 | EQ | Z == 1 | equal |
| 0001 | NE | Z == 0 | not equal |
| 0010 | CS / HS | C == 1 | carry set / unsigned ≥ |
| 0011 | CC / LO | C == 0 | carry clear / unsigned < |
| 0100 | MI | N == 1 | negative |
| 0101 | PL | N == 0 | positive or zero |
| 0110 | VS | V == 1 | signed overflow |
| 0111 | VC | V == 0 | no overflow |
| 1000 | HI | C == 1 and Z == 0 | unsigned > |
| 1001 | LS | C == 0 or Z == 1 | unsigned ≤ |
| 1010 | GE | N == V | signed ≥ |
| 1011 | LT | N != V | signed < |
| 1100 | GT | Z == 0 and N == V | signed > |
| 1101 | LE | Z == 1 or N != V | signed ≤ |
| 1110 | AL | any | always |
| 1111 | NV | any | always (not a true "never") |
Signed comparisons use GE/LT/GT/LE; unsigned ones use HS/LO/HI/LS.
b.cond, ccmp, csel and friends all take these codes.
AL and NV both always execute (there is no real "never" condition). Inverting a condition flips the low bit of the field.Top-level encoding groups (bits 28:25, "op0")
| op0 | Group |
|---|---|
| 0000 | Reserved (0x00000000 is permanently undefined, udf #0) |
| 0010 | SVE instructions |
| 100x | Data processing – immediate (PC-rel, add/sub imm, logical imm, move wide, bitfield, extract) |
| 101x | Branches, exception generation and system instructions |
| x1x0 | Loads and stores |
| x101 | Data processing – register |
| x111 | Data processing – scalar FP and Advanced SIMD |
Every A64 instruction is exactly 32 bits, little-endian, 4-byte aligned. Common field positions: Rd = bits 4:0, Rn = 9:5,
Rm = 20:16, and sf (bit 31) selects 64-bit (1) vs 32-bit (0) operands for most data-processing instructions.
Bitmask (logical) immediates
The immediate of and/orr/eor/ands (and so mov of a constant) is not an arbitrary number. The
N:immr:imms fields encode a repeating pattern: a run of ones of a chosen length, rotated right by immr, replicated to fill the register
at an element size of 2, 4, 8, 16, 32 or 64 bits. So 0xff, 0x5555... and 0xfffffff000000000 are encodable, but 0xff00ff00ff00ff01 is not;
the assembler falls back to mov/movk sequences for those. Values that cannot be formed (such as all-zeros or all-ones) are simply not representable.
Extend and shift options
option (extended register)
000UXTB,001UXTH,010UXTW,011UXTX/LSL100SXTB,101SXTH,110SXTW,111SXTX- Lets you add/subtract a narrow value with zero/sign extension and a 0–4 left shift, and is how SP is addressed.
shift (shifted register)
00LSL,01LSR,10ASR,11ROR (ROR only for logical ops).- Shift amount is a 6-bit immediate (0–63 for X, 0–31 for W).
Addressing modes
- Unsigned offset:
[Xn, #imm](scaled by access size). - Pre-index
[Xn, #imm]!and post-index[Xn], #immwrite back Xn. - Register offset:
[Xn, Rm, ext #amt]. Literal:label(PC-relative).
Common system registers (verified with the assembler)
| Register | op0_op1_CRn_CRm_op2 | Purpose |
|---|---|---|
| NZCV | S3_3_C4_C2_0 | Condition flags (N, Z, C, V) |
| FPCR / FPSR | S3_3_C4_C4_0/1 | FP control and status |
| DAIF | S3_3_C4_C2_1 | Interrupt mask bits (D, A, I, F) |
| CurrentEL | S3_0_C4_C2_2 | Current exception level (bits 3:2) |
| TPIDR_EL0 | S3_3_C13_C0_2 | Thread pointer, writable at EL0 (Linux TLS) |
| TPIDRRO_EL0 | S3_3_C13_C0_3 | Read-only thread pointer (Apple TLS) |
| CNTVCT_EL0 | S3_3_C14_C0_2 | Virtual count (timestamp) |
| CNTFRQ_EL0 | S3_3_C14_C0_0 | Counter frequency |
| MIDR_EL1 | S3_0_C0_C0_0 | Main ID (implementer, part number) |
| MPIDR_EL1 | S3_0_C0_C0_5 | Multiprocessor affinity (core ID) |
| ID_AA64ISAR0_EL1 | S3_0_C0_C6_0 | ISA feature register 0 |
| SCTLR_EL1 | S3_0_C1_C0_0 | System control (MMU, caches, WXN...) |
| TTBR0_EL1 / TTBR1_EL1 | S3_0_C2_C0_0/1 | Translation table base (user / kernel) |
| TCR_EL1 | S3_0_C2_C0_2 | Translation control (page size, VA range) |
| MAIR_EL1 | S3_0_C10_C2_0 | Memory attribute indirection |
| VBAR_EL1 | S3_0_C12_C0_0 | Vector base address (exception table) |
| ESR_EL1 | S3_0_C5_C2_0 | Exception syndrome (fault cause) |
| FAR_EL1 | S3_0_C6_C0_0 | Faulting virtual address |
| ELR_EL1 | S3_0_C4_C0_1 | Exception link register (return address) |
| SPSR_EL1 | S3_0_C4_C0_0 | Saved program status |
| SP_EL0 | S3_0_C4_C1_0 | EL0 stack pointer |
Accessed with
mrs Xt, reg (read) and msr reg, Xt (write). An unknown name can always be written by its numeric
S<op0>_<op1>_C<CRn>_C<CRm>_<op2> form, which is what a disassembler prints when it does not recognise the encoding.Common aliases (what a disassembler prints vs. what is encoded)
| Alias | Real instruction |
|---|---|
| mov Rd, Rm | orr Rd, xzr, Rm |
| mov Rd, #imm | movz / movn / orr (bitmask) |
| mov Rd, sp / mov sp, Rn | add Rd, sp, #0 / add sp, Rn, #0 |
| mvn Rd, Rm | orn Rd, xzr, Rm |
| neg Rd, Rm | sub Rd, xzr, Rm |
| negs Rd, Rm | subs Rd, xzr, Rm |
| ngc Rd, Rm | sbc Rd, xzr, Rm |
| cmp Rn, op | subs xzr, Rn, op |
| cmn Rn, op | adds xzr, Rn, op |
| tst Rn, op | ands xzr, Rn, op |
| lsl / lsr / asr Rd, Rn, #imm | ubfm / ubfm / sbfm |
| ror Rd, Rs, #imm | extr Rd, Rs, Rs, #imm |
| sxtb / sxth / sxtw | sbfm Rd, Rn, #0, #7/15/31 |
| uxtb / uxth | ubfm Rd, Rn, #0, #7/15 |
| ubfx / sbfx / bfi / bfxil | ubfm / sbfm / bfm variants |
| mul Rd, Rn, Rm | madd Rd, Rn, Rm, xzr |
| mneg Rd, Rn, Rm | msub Rd, Rn, Rm, xzr |
| smull / umull | smaddl / umaddl ..., xzr |
| cset Rd, cond | csinc Rd, xzr, xzr, invert(cond) |
| csetm Rd, cond | csinv Rd, xzr, xzr, invert(cond) |
| cinc / cinv / cneg Rd, Rn, cond | csinc / csinv / csneg Rd, Rn, Rn, invert(cond) |
| ret | ret x30 |
Instructions (582 entries)
| Mnemonic | Syntax | Description | Ext. |
|---|---|---|---|
| Arithmetic | |||
| add (imm) | Rd, Rn, #imm12{, lsl #12} |
Rd = Rn + imm. The 12-bit immediate can be shifted left by 12. | Base |
|
31sf1 300 290 28–231 0 0 0 1 0 22sh0 21–10imm12000000010000 9–5Rn00001 4–0Rd00000
Example
add x0, x1, #169100402020 40 00 91 |
|||
| adds (imm) | Rd, Rn, #imm12{, lsl #12} |
Rd = Rn + imm, set NZCV. The 12-bit immediate can be shifted left by 12. | Base |
|
31sf1 300 291 28–231 0 0 0 1 0 22sh0 21–10imm12000000010000 9–5Rn00001 4–0Rd00000
Example
adds x0, x1, #16b100402020 40 00 b1 |
|||
| sub (imm) | Rd, Rn, #imm12{, lsl #12} |
Rd = Rn - imm. The 12-bit immediate can be shifted left by 12. | Base |
|
31sf1 301 290 28–231 0 0 0 1 0 22sh0 21–10imm12000000010000 9–5Rn00001 4–0Rd00000 Example
sub x0, x1, #16d100402020 40 00 d1 |
|||
| subs (imm) | Rd, Rn, #imm12{, lsl #12} |
Rd = Rn - imm, set NZCV. The 12-bit immediate can be shifted left by 12. | Base |
|
31sf1 301 291 28–231 0 0 0 1 0 22sh0 21–10imm12000000010000 9–5Rn00001 4–0Rd00000
Example
subs x0, x1, #16f100402020 40 00 f1 |
|||
| add (shifted) | Rd, Rn, Rm{, shift #amt} |
Same operation with a register operand, optionally shifted (LSL, LSR, ASR). | Base |
|
31sf1 300 290 28–240 1 0 1 1 23–22shift00 210 20–16Rm00010 15–10imm6000011 9–5Rn00001 4–0Rd00000 Example
add x0, x1, x2, lsl #38b020c2020 0c 02 8b |
|||
| adds (shifted) | Rd, Rn, Rm{, shift #amt} |
Same operation with a register operand, optionally shifted (LSL, LSR, ASR). | Base |
|
31sf1 300 291 28–240 1 0 1 1 23–22shift00 210 20–16Rm00010 15–10imm6000011 9–5Rn00001 4–0Rd00000 Example
adds x0, x1, x2, lsl #3ab020c2020 0c 02 ab |
|||
| sub (shifted) | Rd, Rn, Rm{, shift #amt} |
Same operation with a register operand, optionally shifted (LSL, LSR, ASR). | Base |
|
31sf1 301 290 28–240 1 0 1 1 23–22shift00 210 20–16Rm00010 15–10imm6000011 9–5Rn00001 4–0Rd00000
Example
sub x0, x1, x2, lsl #3cb020c2020 0c 02 cb |
|||
| subs (shifted) | Rd, Rn, Rm{, shift #amt} |
Same operation with a register operand, optionally shifted (LSL, LSR, ASR). | Base |
|
31sf1 301 291 28–240 1 0 1 1 23–22shift00 210 20–16Rm00010 15–10imm6000011 9–5Rn00001 4–0Rd00000
Example
subs x0, x1, x2, lsl #3eb020c2020 0c 02 eb |
|||
| add (extended) | Rd, Rn, Wm, extend {#amt} |
Same operation with a zero/sign-extended register operand, shifted left by 0–4. Allows SP as Rn. | Base |
|
31sf1 300 290 28–240 1 0 1 1 23–220 0 211 20–16Rm00010 15–13option110 12–10imm3010 9–5Rn00001 4–0Rd00000 Example
add x0, x1, w2, sxtw #28b22c82020 c8 22 8b |
|||
| adds (extended) | Rd, Rn, Wm, extend {#amt} |
Same operation with a zero/sign-extended register operand, shifted left by 0–4. Allows SP as Rn. | Base |
|
31sf1 300 291 28–240 1 0 1 1 23–220 0 211 20–16Rm00010 15–13option110 12–10imm3010 9–5Rn00001 4–0Rd00000 Example
adds x0, x1, w2, sxtw #2ab22c82020 c8 22 ab |
|||
| sub (extended) | Rd, Rn, Wm, extend {#amt} |
Same operation with a zero/sign-extended register operand, shifted left by 0–4. Allows SP as Rn. | Base |
|
31sf1 301 290 28–240 1 0 1 1 23–220 0 211 20–16Rm00010 15–13option110 12–10imm3010 9–5Rn00001 4–0Rd00000 Example
sub x0, x1, w2, sxtw #2cb22c82020 c8 22 cb |
|||
| subs (extended) | Rd, Rn, Wm, extend {#amt} |
Same operation with a zero/sign-extended register operand, shifted left by 0–4. Allows SP as Rn. | Base |
|
31sf1 301 291 28–240 1 0 1 1 23–220 0 211 20–16Rm00010 15–13option110 12–10imm3010 9–5Rn00001 4–0Rd00000 Example
subs x0, x1, w2, sxtw #2eb22c82020 c8 22 eb |
|||
| adc | Rd, Rn, Rm |
Rd = Rn + Rm + C. | Base |
|
31sf1 300 290 28–211 1 0 1 0 0 0 0 20–16Rm00010 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
adc x0, x1, x29a02002020 00 02 9a |
|||
| adcs | Rd, Rn, Rm |
Add with carry, set NZCV. | Base |
|
31sf1 300 291 28–211 1 0 1 0 0 0 0 20–16Rm00010 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
adcs x0, x1, x2ba02002020 00 02 ba |
|||
| sbc | Rd, Rn, Rm |
Rd = Rn - Rm - 1 + C. | Base |
|
31sf1 301 290 28–211 1 0 1 0 0 0 0 20–16Rm00010 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
sbc x0, x1, x2da02002020 00 02 da |
|||
| sbcs | Rd, Rn, Rm |
Subtract with carry, set NZCV. | Base |
|
31sf1 301 291 28–211 1 0 1 0 0 0 0 20–16Rm00010 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
sbcs x0, x1, x2fa02002020 00 02 fa |
|||
| ngc | Rd, Rm |
Negate with carry: Rd = -Rm - 1 + C (alias of SBC). | Base |
|
31sf1 301 290 28–211 1 0 1 0 0 0 0 20–16Rm00001 15–100 0 0 0 0 0 9–51 1 1 1 1 4–0Rd00000 Example
ngc x0, x1da0103e0e0 03 01 da |
|||
| ngcs | Rd, Rm |
Negate with carry, set flags (alias of SBCS). | Base |
|
31sf1 301 291 28–211 1 0 1 0 0 0 0 20–16Rm00001 15–100 0 0 0 0 0 9–51 1 1 1 1 4–0Rd00000 Example
ngcs x0, x1fa0103e0e0 03 01 fa |
|||
| Logical | |||
| and (imm) | Rd, Rn, #bitmask |
Rd = Rn AND imm. The immediate is a bitmask pattern (see the bitmask section). | Base |
|
31sf1 30–290 0 28–231 0 0 1 0 0 22N1 21–16immr111000 15–10imms000111 9–5Rn00001 4–0Rd00000 Example
and x0, x1, #0xff0092781c2020 1c 78 92 |
|||
| orr (imm) | Rd, Rn, #bitmask |
Rd = Rn OR imm. The immediate is a bitmask pattern (see the bitmask section). | Base |
|
31sf1 30–290 1 28–231 0 0 1 0 0 22N1 21–16immr111000 15–10imms000111 9–5Rn00001 4–0Rd00000
Example
orr x0, x1, #0xff00b2781c2020 1c 78 b2 |
|||
| eor (imm) | Rd, Rn, #bitmask |
Rd = Rn XOR imm. The immediate is a bitmask pattern (see the bitmask section). | Base |
|
31sf1 30–291 0 28–231 0 0 1 0 0 22N1 21–16immr111000 15–10imms000111 9–5Rn00001 4–0Rd00000 Example
eor x0, x1, #0xff00d2781c2020 1c 78 d2 |
|||
| ands (imm) | Rd, Rn, #bitmask |
Rd = Rn AND imm, set NZ. The immediate is a bitmask pattern (see the bitmask section). | Base |
|
31sf1 30–291 1 28–231 0 0 1 0 0 22N1 21–16immr111000 15–10imms000111 9–5Rn00001 4–0Rd00000
Example
ands x0, x1, #0xff00f2781c2020 1c 78 f2 |
|||
| and (shifted) | Rd, Rn, Rm{, shift #amt} |
Rd = Rn AND Rm, Rm optionally shifted (LSL, LSR, ASR, ROR). | Base |
|
31sf1 30–290 0 28–240 1 0 1 0 23–22shift01 210 20–16Rm00010 15–10imm6000100 9–5Rn00001 4–0Rd00000 Example
and x0, x1, x2, lsr #48a42102020 10 42 8a |
|||
| bic (shifted) | Rd, Rn, Rm{, shift #amt} |
Rd = Rn AND NOT Rm, Rm optionally shifted (LSL, LSR, ASR, ROR). | Base |
|
31sf1 30–290 0 28–240 1 0 1 0 23–22shift01 211 20–16Rm00010 15–10imm6000100 9–5Rn00001 4–0Rd00000 Example
bic x0, x1, x2, lsr #48a62102020 10 62 8a |
|||
| orr (shifted) | Rd, Rn, Rm{, shift #amt} |
Rd = Rn OR Rm, Rm optionally shifted (LSL, LSR, ASR, ROR). | Base |
|
31sf1 30–290 1 28–240 1 0 1 0 23–22shift01 210 20–16Rm00010 15–10imm6000100 9–5Rn00001 4–0Rd00000
Example
orr x0, x1, x2, lsr #4aa42102020 10 42 aa |
|||
| orn (shifted) | Rd, Rn, Rm{, shift #amt} |
Rd = Rn OR NOT Rm, Rm optionally shifted (LSL, LSR, ASR, ROR). | Base |
|
31sf1 30–290 1 28–240 1 0 1 0 23–22shift01 211 20–16Rm00010 15–10imm6000100 9–5Rn00001 4–0Rd00000
Example
orn x0, x1, x2, lsr #4aa62102020 10 62 aa |
|||
| eor (shifted) | Rd, Rn, Rm{, shift #amt} |
Rd = Rn XOR Rm, Rm optionally shifted (LSL, LSR, ASR, ROR). | Base |
|
31sf1 30–291 0 28–240 1 0 1 0 23–22shift01 210 20–16Rm00010 15–10imm6000100 9–5Rn00001 4–0Rd00000 Example
eor x0, x1, x2, lsr #4ca42102020 10 42 ca |
|||
| eon (shifted) | Rd, Rn, Rm{, shift #amt} |
Rd = Rn XOR NOT Rm, Rm optionally shifted (LSL, LSR, ASR, ROR). | Base |
|
31sf1 30–291 0 28–240 1 0 1 0 23–22shift01 211 20–16Rm00010 15–10imm6000100 9–5Rn00001 4–0Rd00000 Example
eon x0, x1, x2, lsr #4ca62102020 10 62 ca |
|||
| ands (shifted) | Rd, Rn, Rm{, shift #amt} |
Rd = Rn AND Rm, set NZ, Rm optionally shifted (LSL, LSR, ASR, ROR). | Base |
|
31sf1 30–291 1 28–240 1 0 1 0 23–22shift01 210 20–16Rm00010 15–10imm6000100 9–5Rn00001 4–0Rd00000
Example
ands x0, x1, x2, lsr #4ea42102020 10 42 ea |
|||
| bics (shifted) | Rd, Rn, Rm{, shift #amt} |
Rd = Rn AND NOT Rm, set NZ, Rm optionally shifted (LSL, LSR, ASR, ROR). | Base |
|
31sf1 30–291 1 28–240 1 0 1 0 23–22shift01 211 20–16Rm00010 15–10imm6000100 9–5Rn00001 4–0Rd00000 Example
bics x0, x1, x2, lsr #4ea62102020 10 62 ea |
|||
| Move wide | |||
| movz | Rd, #imm16{, lsl #s} |
Rd = imm16 << (hw × 16), other bits zero. | Base |
|
31sf1 30–291 0 28–231 0 0 1 0 1 22–21hw01 20–5imm160001001000110100 4–0Rd00000 Displayed as Example
movz x0, #0x1234, lsl #16d2a2468080 46 a2 d2 |
|||
| movn | Rd, #imm16{, lsl #s} |
Rd = NOT(imm16 << (hw × 16)). | Base |
|
31sf1 30–290 0 28–231 0 0 1 0 1 22–21hw01 20–5imm160000000000000001 4–0Rd00000 Example
movn x0, #0x1, lsl #1692a0002020 00 a0 92 |
|||
| movk | Rd, #imm16{, lsl #s} |
Insert imm16 at position hw × 16, keeping other bits. | Base |
|
31sf1 30–291 1 28–231 0 0 1 0 1 22–21hw10 20–5imm161011111011101111 4–0Rd00000 A 64-bit constant is typically built with one Example
movk x0, #0xbeef, lsl #32f2d7dde0e0 dd d7 f2 |
|||
| Bitfield and shifts | |||
| sbfm | Rd, Rn, #immr, #imms |
Signed bitfield move: extract and sign-extend a field. | Base |
|
31sf1 30–290 0 28–231 0 0 1 1 0 22N1 21–16immr000100 15–10imms001011 9–5Rn00001 4–0Rd00000 Aliases: Example
sbfm x0, x1, #4, #1193442c2020 2c 44 93 |
|||
| bfm | Rd, Rn, #immr, #imms |
Bitfield move: copy a field into Rd, keeping the other bits. | Base |
|
31sf1 30–290 1 28–231 0 0 1 1 0 22N1 21–16immr000100 15–10imms001011 9–5Rn00001 4–0Rd00000 Aliases: Example
bfm x0, x1, #4, #11b3442c2020 2c 44 b3 |
|||
| ubfm | Rd, Rn, #immr, #imms |
Unsigned bitfield move: extract and zero-extend a field. | Base |
|
31sf1 30–291 0 28–231 0 0 1 1 0 22N1 21–16immr000100 15–10imms001011 9–5Rn00001 4–0Rd00000 Aliases: Example
ubfm x0, x1, #4, #11d3442c2020 2c 44 d3 |
|||
| ubfx | Rd, Rn, #lsb, #width |
Extract width bits starting at lsb, zero-extended (alias of UBFM). | Base |
|
31sf1 30–291 0 28–231 0 0 1 1 0 22N1 21–16immr001000 15–10imms001011 9–5Rn00001 4–0Rd00000 Example
ubfx x0, x1, #8, #4d3482c2020 2c 48 d3 |
|||
| sbfx | Rd, Rn, #lsb, #width |
Extract width bits starting at lsb, sign-extended (alias of SBFM). | Base |
|
31sf1 30–290 0 28–231 0 0 1 1 0 22N1 21–16immr001000 15–10imms001011 9–5Rn00001 4–0Rd00000 Example
sbfx x0, x1, #8, #493482c2020 2c 48 93 |
|||
| bfi | Rd, Rn, #lsb, #width |
Insert the low width bits of Rn into Rd at lsb (alias of BFM). | Base |
|
31sf1 30–290 1 28–231 0 0 1 1 0 22N1 21–16immr111000 15–10imms000011 9–5Rn00001 4–0Rd00000 Example
bfi x0, x1, #8, #4b3780c2020 0c 78 b3 |
|||
| lsl (imm) | Rd, Rn, #shift |
Logical shift left by an immediate (alias of UBFM). | Base |
|
31sf1 30–291 0 28–231 0 0 1 1 0 22N1 21–16immr111101 15–10imms111100 9–5Rn00001 4–0Rd00000 Example
lsl x0, x1, #3d37df02020 f0 7d d3 |
|||
| lsr (imm) | Rd, Rn, #shift |
Logical shift right by an immediate (alias of UBFM). | Base |
|
31sf1 30–291 0 28–231 0 0 1 1 0 22N1 21–16immr000011 15–10imms111111 9–5Rn00001 4–0Rd00000 Example
lsr x0, x1, #3d343fc2020 fc 43 d3 |
|||
| asr (imm) | Rd, Rn, #shift |
Arithmetic shift right by an immediate (alias of SBFM). | Base |
|
31sf1 30–290 0 28–231 0 0 1 1 0 22N1 21–16immr000011 15–10imms111111 9–5Rn00001 4–0Rd00000 Example
asr x0, x1, #39343fc2020 fc 43 93 |
|||
| sxtw | Xd, Wn |
Sign-extend a word to 64 bits (alias of SBFM). | Base |
|
311 30–290 0 28–231 0 0 1 1 0 221 21–160 0 0 0 0 0 15–100 1 1 1 1 1 9–5Rn00001 4–0Rd00000 Example
sxtw x0, w193407c2020 7c 40 93 |
|||
| extr | Rd, Rn, Rm, #lsb |
Extract a register-width field from the concatenation Rn:Rm starting at lsb. | Base |
|
31sf1 30–290 0 28–231 0 0 1 1 1 22N1 210 20–16Rm00010 15–10imms001100 9–5Rn00001 4–0Rd00000
Example
extr x0, x1, x2, #1293c2302020 30 c2 93 |
|||
| lslv | Rd, Rn, Rm |
Shift left by Rm modulo the register width. | Base |
|
31sf1 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–120 0 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Usually displayed as Example
lslv x0, x1, x29ac2202020 20 c2 9a |
|||
| lsrv | Rd, Rn, Rm |
Shift right (logical) by Rm modulo the register width. | Base |
|
31sf1 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–120 0 1 0 11–100 1 9–5Rn00001 4–0Rd00000 Usually displayed as Example
lsrv x0, x1, x29ac2242020 24 c2 9a |
|||
| asrv | Rd, Rn, Rm |
Shift right (arithmetic) by Rm modulo the register width. | Base |
|
31sf1 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–120 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Usually displayed as Example
asrv x0, x1, x29ac2282020 28 c2 9a |
|||
| rorv | Rd, Rn, Rm |
Shift right (rotate) by Rm modulo the register width. | Base |
|
31sf1 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–120 0 1 0 11–101 1 9–5Rn00001 4–0Rd00000 Usually displayed as Example
rorv x0, x1, x29ac22c2020 2c c2 9a |
|||
| Multiply and divide | |||
| madd | Rd, Rn, Rm, Ra |
Rd = Ra + Rn × Rm. | Base |
|
31sf1 30–290 0 28–241 1 0 1 1 23–210 0 0 20–16Rm00010 150 14–10Ra00011 9–5Rn00001 4–0Rd00000
Example
madd x0, x1, x2, x39b020c2020 0c 02 9b |
|||
| msub | Rd, Rn, Rm, Ra |
Rd = Ra - Rn × Rm. | Base |
|
31sf1 30–290 0 28–241 1 0 1 1 23–210 0 0 20–16Rm00010 151 14–10Ra00011 9–5Rn00001 4–0Rd00000
Example
msub x0, x1, x2, x39b028c2020 8c 02 9b |
|||
| smaddl | Xd, Wn, Wm, Xa |
Xd = Xa + sext(Wn) × sext(Wm). | Base |
|
311 30–290 0 28–241 1 0 1 1 23–210 0 1 20–16Rm00010 150 14–10Ra00011 9–5Rn00001 4–0Rd00000
Example
smaddl x0, w1, w2, x39b220c2020 0c 22 9b |
|||
| umaddl | Xd, Wn, Wm, Xa |
Xd = Xa + zext(Wn) × zext(Wm). | Base |
|
311 30–290 0 28–241 1 0 1 1 23–211 0 1 20–16Rm00010 150 14–10Ra00011 9–5Rn00001 4–0Rd00000
Example
umaddl x0, w1, w2, x39ba20c2020 0c a2 9b |
|||
| smulh | Xd, Xn, Xm |
High 64 bits of the signed 128-bit product. | Base |
|
311 30–290 0 28–241 1 0 1 1 23–210 1 0 20–16Rm00010 150 14–101 1 1 1 1 9–5Rn00001 4–0Rd00000 Seen in division by a constant (magic-number multiplication). Example
smulh x0, x1, x29b427c2020 7c 42 9b |
|||
| umulh | Xd, Xn, Xm |
High 64 bits of the unsigned 128-bit product. | Base |
|
311 30–290 0 28–241 1 0 1 1 23–211 1 0 20–16Rm00010 150 14–101 1 1 1 1 9–5Rn00001 4–0Rd00000 Example
umulh x0, x1, x29bc27c2020 7c c2 9b |
|||
| sdiv | Rd, Rn, Rm |
Signed division, rounds toward zero. Division by zero gives 0 (no trap). | Base |
|
31sf1 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–110 0 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
sdiv x0, x1, x29ac20c2020 0c c2 9a |
|||
| udiv | Rd, Rn, Rm |
Unsigned division. Division by zero gives 0. | Base |
|
31sf1 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–110 0 0 0 1 100 9–5Rn00001 4–0Rd00000 Example
udiv x0, x1, x29ac2082020 08 c2 9a |
|||
| Bit operations | |||
| rbit | Rd, Rn |
Reverse the bit order. | Base |
|
31sf1 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 0 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
rbit x0, x1dac0002020 00 c0 da |
|||
| rev16 | Rd, Rn |
Reverse bytes in each halfword. | Base |
|
31sf1 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 0 15–100 0 0 0 0 1 9–5Rn00001 4–0Rd00000 Example
rev16 x0, x1dac0042020 04 c0 da |
|||
| clz | Rd, Rn |
Count leading zero bits. | Base |
|
31sf1 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 0 15–100 0 0 1 0 0 9–5Rn00001 4–0Rd00000 Example
clz x0, x1dac0102020 10 c0 da |
|||
| cls | Rd, Rn |
Count leading bits equal to the sign bit (excluding it). | Base |
|
31sf1 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 0 15–100 0 0 1 0 1 9–5Rn00001 4–0Rd00000 Example
cls x0, x1dac0142020 14 c0 da |
|||
| rev32 | Xd, Xn |
Reverse bytes in each word of a 64-bit register. | Base |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 0 15–100 0 0 0 1 0 9–5Rn00001 4–0Rd00000 Example
rev32 x0, x1dac0082020 08 c0 da |
|||
| rev | Rd, Rn |
Reverse all bytes (endianness swap). opc is 10 for W, 11 for X. | Base |
|
31sf1 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 0 15–120 0 0 0 11–10opc11 9–5Rn00001 4–0Rd00000 Example
rev x0, x1dac00c2020 0c c0 da |
|||
| Conditional | |||
| csel | Rd, Rn, Rm, cond |
Rd = cond ? Rn : Rm. | Base |
|
31sf1 300 290 28–211 1 0 1 0 1 0 0 20–16Rm00010 15–12cond0001 11–100 0 9–5Rn00001 4–0Rd00000 Example
csel x0, x1, x2, ne9a82102020 10 82 9a |
|||
| csinc | Rd, Rn, Rm, cond |
Rd = cond ? Rn : Rm + 1. | Base |
|
31sf1 300 290 28–211 1 0 1 0 1 0 0 20–16Rm00010 15–12cond0001 11–100 1 9–5Rn00001 4–0Rd00000
Example
csinc x0, x1, x2, ne9a82142020 14 82 9a |
|||
| csinv | Rd, Rn, Rm, cond |
Rd = cond ? Rn : NOT Rm. | Base |
|
31sf1 301 290 28–211 1 0 1 0 1 0 0 20–16Rm00010 15–12cond0001 11–100 0 9–5Rn00001 4–0Rd00000
Example
csinv x0, x1, x2, neda82102020 10 82 da |
|||
| csneg | Rd, Rn, Rm, cond |
Rd = cond ? Rn : -Rm. | Base |
|
31sf1 301 290 28–211 1 0 1 0 1 0 0 20–16Rm00010 15–12cond0001 11–100 1 9–5Rn00001 4–0Rd00000
Example
csneg x0, x1, x2, neda82142020 14 82 da |
|||
| ccmp (reg) | Rn, Rm, #nzcv, cond |
If cond holds, set flags from Rn - Rm; otherwise set NZCV to #nzcv. | Base |
|
31sf1 301 291 28–211 1 0 1 0 0 1 0 20–16Rm00001 15–12cond0001 110 100 9–5Rn00000 40 3–0nzcv0100 Chains comparisons without branches: Example
ccmp x0, x1, #4, nefa41100404 10 41 fa |
|||
| ccmp (imm) | Rn, #imm5, #nzcv, cond |
Same with a 5-bit immediate. | Base |
|
31sf1 301 291 28–211 1 0 1 0 0 1 0 20–16imm500011 15–12cond0000 111 100 9–5Rn00000 40 3–0nzcv0000 Example
ccmp x0, #3, #0, eqfa43080000 08 43 fa |
|||
| ccmn (reg) | Rn, Rm, #nzcv, cond |
If cond holds, set flags from Rn + Rm; otherwise set NZCV to #nzcv. | Base |
|
31sf1 300 291 28–211 1 0 1 0 0 1 0 20–16Rm00001 15–12cond0001 110 100 9–5Rn00000 40 3–0nzcv0100 Example
ccmn x0, x1, #4, neba41100404 10 41 ba |
|||
| rmif | Xn, #shift, #mask |
Rotate Xn right by #shift and write selected bits into NZCV (mask picks which flags). | FlagM |
|
311 300 291 28–211 1 0 1 0 0 0 0 20–15imm6000100 14–100 0 0 0 1 9–5Rn00000 40 3–0mask1111 Example
rmif x0, #4, #15ba02040f0f 04 02 ba |
|||
| setf8 | Wn |
Set N and Z from the low 8 bits of Wn (for narrow adds). | FlagM |
|
310 300 291 28–211 1 0 1 0 0 0 0 20–150 0 0 0 0 0 140 13–100 0 1 0 9–5Rn00000 40 3–01 1 0 1 Example
setf8 w03a00080d0d 08 00 3a |
|||
| setf16 | Wn |
Set N and Z from the low 16 bits of Wn. | FlagM |
|
310 300 291 28–211 1 0 1 0 0 0 0 20–150 0 0 0 0 0 141 13–100 0 1 0 9–5Rn00000 40 3–01 1 0 1 Example
setf16 w03a00480d0d 48 00 3a |
|||
| cfinv | |
Invert the carry flag. | Base |
|
31–121 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 11–80 0 0 0 7–50 0 0 4–01 1 1 1 1 Example
cfinvd500401f1f 40 00 d5 |
|||
| axflag | |
Convert Arm NZCV to the alternative (x86-like) floating-point flag format. | Base |
|
31–121 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 11–80 0 0 0 7–50 1 0 4–01 1 1 1 1 Example
axflagd500405f5f 40 00 d5 |
|||
| xaflag | |
Convert alternative floating-point flags back to Arm NZCV. | Base |
|
31–121 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 11–80 0 0 0 7–50 0 1 4–01 1 1 1 1 Example
xaflagd500403f3f 40 00 d5 |
|||
| PC-relative addressing | |||
| adr | Xd, label |
Xd = PC + offset (±1 MiB). | Base |
|
310 30–29immlo00 28–241 0 0 0 0 23–5immhi0000000000100000000 4–0Rd00000 Example
adr x0, #10241000200000 20 00 10 |
|||
| adrp | Xd, label |
Xd = (PC & ~0xfff) + (offset << 12): address of a 4 KiB page (±4 GiB). | Base |
|
311 30–29immlo01 28–241 0 0 0 0 23–5immhi0000000000000000000 4–0Rd00000 Followed by Example
adrp x0, #4096b000000000 00 00 b0 |
|||
| Branches | |||
| b | label |
Branch to PC + imm26 × 4 (±128 MiB). | Base |
|
310 30–260 0 1 0 1 25–0imm2600000000000000000000010000 Example
b #641400001010 00 00 14 |
|||
| bl | label |
Branch with link: X30 = PC + 4, then branch. | Base |
|
311 30–260 0 1 0 1 25–0imm2600000000000000000000010000 Example
bl #649400001010 00 00 94 |
|||
| b.cond | label |
Branch if the condition holds (±1 MiB). | Base |
|
31–250 1 0 1 0 1 0 240 23–5imm190000000000000010000 40 3–0cond0001 Example
b.ne #645400020101 02 00 54 |
|||
| cbz | Rt, label |
Branch if Rt is zero. Flags unchanged. | Base |
|
31sf1 30–250 1 1 0 1 0 240 23–5imm190000000000000010000 4–0Rt00000 Example
cbz x0, #64b400020000 02 00 b4 |
|||
| cbnz | Rt, label |
Branch if Rt is non-zero. | Base |
|
31sf1 30–250 1 1 0 1 0 241 23–5imm190000000000000010000 4–0Rt00000 Example
cbnz x0, #64b500020000 02 00 b5 |
|||
| tbz | Rt, #bit, label |
Branch if bit #bit of Rt is zero (±32 KiB). | Base |
|
31b51 30–250 1 1 0 1 1 240 23–19b4000001 18–5imm1400000000010000 4–0Rt00000 Example
tbz x0, #33, #64b608020000 02 08 b6 |
|||
| tbnz | Rt, #bit, label |
Branch if bit #bit of Rt is one. | Base |
|
31b50 30–250 1 1 0 1 1 241 23–19b4000011 18–5imm1400000000010000 4–0Rt00000 Example
tbnz w0, #3, #643718020000 02 18 37 |
|||
| br | Xn |
Branch to the address in Xn. | Base |
|
31–251 1 0 1 0 1 1 240 230 22–210 0 20–161 1 1 1 1 15–120 0 0 0 110 100 9–5Rn10000 4–00 0 0 0 0 PLT stubs end with Example
br x16d61f020000 02 1f d6 |
|||
| blr | Xn |
Call the address in Xn: X30 = PC + 4. | Base |
|
31–251 1 0 1 0 1 1 240 230 22–210 1 20–161 1 1 1 1 15–120 0 0 0 110 100 9–5Rn01000 4–00 0 0 0 0 Example
blr x8d63f010000 01 3f d6 |
|||
| ret | {Xn} |
Return to the address in Xn (default X30). Hints the return-address predictor. | Base |
|
31–251 1 0 1 0 1 1 240 230 22–211 0 20–161 1 1 1 1 15–120 0 0 0 110 100 9–5Rn11110 4–00 0 0 0 0
Example
retd65f03c0c0 03 5f d6 |
|||
| braa | Xn, Xm |
Authenticate Xn with key A (modifier Xm), then branch to it. | PAC |
|
31–251 1 0 1 0 1 1 241 230 22–210 0 20–161 1 1 1 1 15–110 0 0 0 1 100 9–5Rn00000 4–0Rm00001 Example
braa x0, x1d71f080101 08 1f d7 |
|||
| brab | Xn, Xm |
Authenticate with key B, then branch. | PAC |
|
31–251 1 0 1 0 1 1 241 230 22–210 0 20–161 1 1 1 1 15–110 0 0 0 1 101 9–5Rn00000 4–0Rm00001 Example
brab x0, x1d71f0c0101 0c 1f d7 |
|||
| blraa | Xn, Xm |
Authenticate (key A) then branch with link. | PAC |
|
31–251 1 0 1 0 1 1 241 230 22–210 1 20–161 1 1 1 1 15–110 0 0 0 1 100 9–5Rn00000 4–0Rm00001 Example
blraa x0, x1d73f080101 08 3f d7 |
|||
| blrab | Xn, Xm |
Authenticate (key B) then branch with link. | PAC |
|
31–251 1 0 1 0 1 1 241 230 22–210 1 20–161 1 1 1 1 15–110 0 0 0 1 101 9–5Rn00000 4–0Rm00001 Example
blrab x0, x1d73f0c0101 0c 3f d7 |
|||
| braaz | Xn |
Authenticate Xn (key A, modifier zero) then branch. | PAC |
|
31–251 1 0 1 0 1 1 240 23–210 0 0 20–161 1 1 1 1 15–110 0 0 0 1 100 9–5Rn00000 4–01 1 1 1 1 Example
braaz x0d61f081f1f 08 1f d6 |
|||
| blraaz | Xn |
Authenticate (key A, zero) then branch with link. | PAC |
|
31–251 1 0 1 0 1 1 240 23–210 0 1 20–161 1 1 1 1 15–110 0 0 0 1 100 9–5Rn00000 4–01 1 1 1 1 Example
blraaz x0d63f081f1f 08 3f d6 |
|||
| retaa | |
Authenticate LR with key A and SP, then return. Pairs with paciasp. | PAC |
|
31–251 1 0 1 0 1 1 240 230 22–211 0 20–161 1 1 1 1 15–110 0 0 0 1 100 9–51 1 1 1 1 4–01 1 1 1 1 Example
retaad65f0bffff 0b 5f d6 |
|||
| retab | |
Authenticate LR with key B and SP, then return. | PAC |
|
31–251 1 0 1 0 1 1 240 230 22–211 0 20–161 1 1 1 1 15–110 0 0 0 1 101 9–51 1 1 1 1 4–01 1 1 1 1 Example
retabd65f0fffff 0f 5f d6 |
|||
| eret | |
Exception return: restore PC from ELR_ELx and PSTATE from SPSR_ELx. | Base |
|
31–251 1 0 1 0 1 1 240 23–211 0 0 20–161 1 1 1 1 15–120 0 0 0 110 100 9–51 1 1 1 1 4–00 0 0 0 0 Example
eretd69f03e0e0 03 9f d6 |
|||
| eretaa | |
Authenticated exception return (key A). | PAC |
|
31–251 1 0 1 0 1 1 240 23–211 0 0 20–161 1 1 1 1 15–120 0 0 0 111 100 9–51 1 1 1 1 4–01 1 1 1 1 Example
eretaad69f0bffff 0b 9f d6 |
|||
| drps | |
Debug restore process state. | Base |
|
31–251 1 0 1 0 1 1 240 23–211 0 1 20–161 1 1 1 1 15–120 0 0 0 110 100 9–51 1 1 1 1 4–00 0 0 0 0 Example
drpsd6bf03e0e0 03 bf d6 |
|||
| udf | #imm16 |
Permanently undefined: always raises an Undefined Instruction exception. | Base |
|
31–160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15–0imm160000000000000000
Example
udf #00000000000 00 00 00 |
|||
| Loads and stores | |||
| str (imm) | Rt, [Xn, #off] |
Store a register. Offset is scaled by the access size (0–32760 for X). | Base |
|
31–30size11 29–271 1 1 260 25–240 1 23–220 0 21–10imm12000000000010 9–5Rn00001 4–0Rt00000 Example
str x0, [x1, #16]f900082020 08 00 f9 |
|||
| ldr (imm) | Rt, [Xn, #off] |
Load a register, zero-extended. | Base |
|
31–30size11 29–271 1 1 260 25–240 1 23–220 1 21–10imm12000000000010 9–5Rn00001 4–0Rt00000 Example
ldr x0, [x1, #16]f940082020 08 40 f9 |
|||
| strb | Wt, [Xn, #off] |
Store a byte. | Base |
|
31–300 0 29–271 1 1 260 25–240 1 23–220 0 21–10imm12000000000100 9–5Rn00001 4–0Rt00000 Example
strb w0, [x1, #4]3900102020 10 00 39 |
|||
| ldrb | Wt, [Xn, #off] |
Load a byte, zero-extended. | Base |
|
31–300 0 29–271 1 1 260 25–240 1 23–220 1 21–10imm12000000000100 9–5Rn00001 4–0Rt00000 Example
ldrb w0, [x1, #4]3940102020 10 40 39 |
|||
| strh | Wt, [Xn, #off] |
Store a halfword. | Base |
|
31–300 1 29–271 1 1 260 25–240 1 23–220 0 21–10imm12000000000010 9–5Rn00001 4–0Rt00000 Example
strh w0, [x1, #4]7900082020 08 00 79 |
|||
| ldrh | Wt, [Xn, #off] |
Load a halfword, zero-extended. | Base |
|
31–300 1 29–271 1 1 260 25–240 1 23–220 1 21–10imm12000000000010 9–5Rn00001 4–0Rt00000 Example
ldrh w0, [x1, #4]7940082020 08 40 79 |
|||
| ldrsw | Xt, [Xn, #off] |
Load a word, sign-extended to 64 bits. | Base |
|
31–301 0 29–271 1 1 260 25–240 1 23–221 0 21–10imm12000000000001 9–5Rn00001 4–0Rt00000 Example
ldrsw x0, [x1, #4]b980042020 04 80 b9 |
|||
| ldrsb | Rt, [Xn, #off] |
Load a byte, sign-extended (to W if opc bit set, else X). | Base |
|
31–300 0 29–271 1 1 260 25–240 1 231 22opc00 21–10imm12000000000100 9–5Rn00001 4–0Rt00000 Example
ldrsb x0, [x1, #4]3980102020 10 80 39 |
|||
| ldrsh | Rt, [Xn, #off] |
Load a halfword, sign-extended. | Base |
|
31–300 1 29–271 1 1 260 25–240 1 231 22opc00 21–10imm12000000000010 9–5Rn00001 4–0Rt00000 Example
ldrsh x0, [x1, #4]7980082020 08 80 79 |
|||
| str (pre) | Rt, [Xn, #off]! |
Pre-indexed: Xn += off, then store. Writes Xn back. | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 0 210 20–12imm9000010000 11–101 1 9–5Rn00001 4–0Rt00000 Example
str x0, [x1, #16]!f8010c2020 0c 01 f8 |
|||
| str (post) | Rt, [Xn], #off |
Post-indexed: store, then Xn += off. | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 0 210 20–12imm9000010000 11–100 1 9–5Rn00001 4–0Rt00000 Example
str x0, [x1], #16f801042020 04 01 f8 |
|||
| ldr (pre) | Rt, [Xn, #off]! |
Pre-indexed load with writeback. | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 1 210 20–12imm9000010000 11–101 1 9–5Rn00001 4–0Rt00000 Example
ldr x0, [x1, #16]!f8410c2020 0c 41 f8 |
|||
| ldr (post) | Rt, [Xn], #off |
Post-indexed load with writeback. | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 1 210 20–12imm9000010000 11–100 1 9–5Rn00001 4–0Rt00000 Example
ldr x0, [x1], #16f841042020 04 41 f8 |
|||
| str (reg) | Rt, [Xn, Rm{, ext}] |
Store with a register offset, optionally extended and scaled. | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 0 211 20–16Rm00010 15–13option011 12S1 11–101 0 9–5Rn00001 4–0Rt00000 Example
str x0, [x1, x2, lsl #3]f822782020 78 22 f8 |
|||
| ldr (reg) | Rt, [Xn, Rm{, ext}] |
Load with a register offset. | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 1 211 20–16Rm00010 15–13option011 12S1 11–101 0 9–5Rn00001 4–0Rt00000 Example
ldr x0, [x1, x2, lsl #3]f862782020 78 62 f8 |
|||
| ldr (literal) | Rt, label |
Load a register from PC + imm19 × 4 (±1 MiB). | Base |
|
31–30opc01 29–270 1 1 260 25–240 0 23–5imm190000000000100000000 4–0Rt00000 Example
ldr x0, #10245800200000 20 00 58 |
|||
| stur | Rt, [Xn, #off] |
Store with an unscaled signed 9-bit offset (-256..255). | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 0 210 20–12imm9111111000 11–100 0 9–5Rn00001 4–0Rt00000 Example
stur x0, [x1, #-8]f81f802020 80 1f f8 |
|||
| ldur | Rt, [Xn, #off] |
Load with an unscaled signed offset. | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 1 210 20–12imm9111111000 11–100 0 9–5Rn00001 4–0Rt00000 Example
ldur x0, [x1, #-8]f85f802020 80 5f f8 |
|||
| stp | Rt, Rt2, [Xn, #off] |
Store a pair of registers. Offset scaled by the register size. | Base |
|
31–30opc10 29–271 0 1 260 25–230 1 0 220 21–15imm70000010 14–10Rt200001 9–5Rn11111 4–0Rt00000
Example
stp x0, x1, [sp, #16]a90107e0e0 07 01 a9 |
|||
| ldp | Rt, Rt2, [Xn, #off] |
Load a pair of registers. | Base |
|
31–30opc10 29–271 0 1 260 25–230 1 0 221 21–15imm70000010 14–10Rt200001 9–5Rn11111 4–0Rt00000 Example
ldp x0, x1, [sp, #16]a94107e0e0 07 41 a9 |
|||
| stp (pre) | Rt, Rt2, [Xn, #off]! |
Pre-indexed store pair with writeback. | Base |
|
31–30opc10 29–271 0 1 260 25–230 1 1 220 21–15imm71111100 14–10Rt211110 9–5Rn11111 4–0Rt11101 Example
stp x29, x30, [sp, #-32]!a9be7bfdfd 7b be a9 |
|||
| ldp (post) | Rt, Rt2, [Xn], #off |
Post-indexed load pair with writeback. | Base |
|
31–30opc10 29–271 0 1 260 25–230 0 1 221 21–15imm70000100 14–10Rt211110 9–5Rn11111 4–0Rt11101 Example
ldp x29, x30, [sp], #32a8c27bfdfd 7b c2 a8 |
|||
| ldpsw | Xt, Xt2, [Xn, #off] |
Load a pair of words, each sign-extended to 64 bits. | Base |
|
31–300 1 29–271 0 1 260 25–230 1 0 221 21–15imm70000010 14–10Rt200001 9–5Rn00010 4–0Rt00000 Example
ldpsw x0, x1, [x2, #8]6941044040 04 41 69 |
|||
| stnp | Rt, Rt2, [Xn, #off] |
Store pair with a non-temporal hint (bypass caches). | Base |
|
31–30opc10 29–271 0 1 260 25–230 0 0 220 21–15imm70000010 14–10Rt200001 9–5Rn11111 4–0Rt00000 Example
stnp x0, x1, [sp, #16]a80107e0e0 07 01 a8 |
|||
| ldtr | Rt, [Xn, #off] |
Load as if at EL0 (unprivileged access checks). | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 1 210 20–12imm9000001000 11–101 0 9–5Rn00001 4–0Rt00000 Example
ldtr x0, [x1, #8]f840882020 88 40 f8 |
|||
| sttr | Rt, [Xn, #off] |
Store as if at EL0. | Base |
|
31–30size11 29–271 1 1 260 25–240 0 23–220 0 210 20–12imm9000001000 11–101 0 9–5Rn00001 4–0Rt00000 Example
sttr x0, [x1, #8]f800882020 88 00 f8 |
|||
| prfm (imm) | prfop, [Xn, #off] |
Prefetch memory. Rt encodes target (PLD/PLI/PST), policy (L1/L2/L3) and temporality. | Base |
|
31–301 1 29–271 1 1 260 25–240 1 23–221 0 21–10imm12000000001000 9–5Rn00000 4–0Rt00000 Example
prfm pldl1keep, [x0, #64]f980200000 20 80 f9 |
|||
| prfm (literal) | prfop, label |
Prefetch from a PC-relative address. | Base |
|
31–301 1 29–270 1 1 260 25–240 0 23–5imm190000000000100000000 4–0Rt00000 Example
prfm pldl1keep, #1024d800200000 20 00 d8 |
|||
| ldapur | Rt, [Xn, #off] |
Load-acquire (RCpc) with an unscaled offset. | RCpc |
|
31–30size11 29–240 1 1 0 0 1 23–220 1 210 20–12imm9000001000 11–100 0 9–5Rn00001 4–0Rt00000 Example
ldapur x0, [x1, #8]d940802020 80 40 d9 |
|||
| stlur | Rt, [Xn, #off] |
Store-release (RCpc) with an unscaled offset. | RCpc |
|
31–30size11 29–240 1 1 0 0 1 23–220 0 210 20–12imm9000001000 11–100 0 9–5Rn00001 4–0Rt00000 Example
stlur x0, [x1, #8]d900802020 80 00 d9 |
|||
| casp | Rs, Rs+1, Rt, Rt+1, [Xn] |
Compare-and-swap of a register pair (for 128-bit CAS). | LSE |
|
310 30sz1 29–230 0 1 0 0 0 0 220 211 20–16Rs00000 150 14–101 1 1 1 1 9–5Rn00100 4–0Rt00010 Example
casp x0, x1, x2, x3, [x4]48207c8282 7c 20 48 |
|||
| ldxrb | Wt, [Xn] |
Load-exclusive byte. | Base |
|
31–300 0 29–240 0 1 0 0 0 230 221 210 20–161 1 1 1 1 150 14–101 1 1 1 1 9–5Rn00001 4–0Rt00000 Byte/halfword/word are size variants of the exclusive and atomic instructions. Example
ldxrb w0, [x1]085f7c2020 7c 5f 08 |
|||
| ldarb | Wt, [Xn] |
Load-acquire byte. | Base |
|
31–300 0 29–240 0 1 0 0 0 231 221 210 20–161 1 1 1 1 151 14–101 1 1 1 1 9–5Rn00001 4–0Rt00000 Example
ldarb w0, [x1]08dffc2020 fc df 08 |
|||
| stlrb | Wt, [Xn] |
Store-release byte. | Base |
|
31–300 0 29–240 0 1 0 0 0 231 220 210 20–161 1 1 1 1 151 14–101 1 1 1 1 9–5Rn00001 4–0Rt00000 Example
stlrb w0, [x1]089ffc2020 fc 9f 08 |
|||
| Exclusive and ordered | |||
| ldxr | Rt, [Xn] |
Load-exclusive: set a monitor on the address. | Base |
|
31–30size11 29–240 0 1 0 0 0 230 221 210 20–161 1 1 1 1 150 14–101 1 1 1 1 9–5Rn00001 4–0Rt00000 Example
ldxr x0, [x1]c85f7c2020 7c 5f c8 |
|||
| stxr | Ws, Rt, [Xn] |
Store-exclusive: Ws = 0 if the monitor was still set (success), 1 otherwise. | Base |
|
31–30size11 29–240 0 1 0 0 0 230 220 210 20–16Rs00010 150 14–101 1 1 1 1 9–5Rn00001 4–0Rt00000 A lock-free loop is Example
stxr w2, x0, [x1]c8027c2020 7c 02 c8 |
|||
| ldaxr | Rt, [Xn] |
Load-exclusive with acquire ordering. | Base |
|
31–30size11 29–240 0 1 0 0 0 230 221 210 20–161 1 1 1 1 151 14–101 1 1 1 1 9–5Rn00001 4–0Rt00000 Example
ldaxr x0, [x1]c85ffc2020 fc 5f c8 |
|||
| stlxr | Ws, Rt, [Xn] |
Store-exclusive with release ordering. | Base |
|
31–30size11 29–240 0 1 0 0 0 230 220 210 20–16Rs00010 151 14–101 1 1 1 1 9–5Rn00001 4–0Rt00000 Example
stlxr w2, x0, [x1]c802fc2020 fc 02 c8 |
|||
| ldxp | Rt, Rt2, [Xn] |
Load-exclusive pair (sz picks W or X). | Base |
|
311 30sz1 29–240 0 1 0 0 0 230 221 211 20–16Rs11111 150 14–10Rt200001 9–5Rn00010 4–0Rt00000 Example
ldxp x0, x1, [x2]c87f044040 04 7f c8 |
|||
| stxp | Ws, Rt, Rt2, [Xn] |
Store-exclusive pair. | Base |
|
311 30sz1 29–240 0 1 0 0 0 230 220 211 20–16Rs00011 150 14–10Rt200001 9–5Rn00010 4–0Rt00000 Example
stxp w3, x0, x1, [x2]c823044040 04 23 c8 |
|||
| ldar | Rt, [Xn] |
Load-acquire: later accesses cannot be reordered before it. | Base |
|
31–30size11 29–240 0 1 0 0 0 231 221 210 20–161 1 1 1 1 151 14–101 1 1 1 1 9–5Rn00001 4–0Rt00000 Example
ldar x0, [x1]c8dffc2020 fc df c8 |
|||
| stlr | Rt, [Xn] |
Store-release: earlier accesses cannot be reordered after it. | Base |
|
31–30size11 29–240 0 1 0 0 0 231 220 210 20–161 1 1 1 1 151 14–101 1 1 1 1 9–5Rn00001 4–0Rt00000 Example
stlr x0, [x1]c89ffc2020 fc 9f c8 |
|||
| ldapr | Rt, [Xn] |
Load-acquire with RCpc semantics (weaker, matches C++ acquire). | RCpc |
|
31–30size11 29–271 1 1 260 25–240 0 231 220 211 20–161 1 1 1 1 151 141 13–120 0 11–100 0 9–5Rn00001 4–0Rt00000 Example
ldapr x0, [x1]f8bfc02020 c0 bf f8 |
|||
| Atomics (LSE) | |||
| ldadd | Rs, Rt, [Xn] |
Atomic add: Rt = old value, memory = old add Rs. A/R bits add acquire/release (ldadda, ldaddl, ldaddal). |
LSE |
|
31–30size11 29–271 1 1 260 25–240 0 23A0 22R0 211 20–16Rs00000 150 14–120 0 0 11–100 0 9–5Rn00010 4–0Rt00001
Example
ldadd x0, x1, [x2]f820004141 00 20 f8 |
|||
| ldclr | Rs, Rt, [Xn] |
Atomic bit-clear (AND NOT): Rt = old value, memory = old bit-clear Rs. A/R bits add acquire/release (ldclra, ldclrl, ldclral). |
LSE |
|
31–30size11 29–271 1 1 260 25–240 0 23A0 22R0 211 20–16Rs00000 150 14–120 0 1 11–100 0 9–5Rn00010 4–0Rt00001
Example
ldclr x0, x1, [x2]f820104141 10 20 f8 |
|||
| ldeor | Rs, Rt, [Xn] |
Atomic XOR: Rt = old value, memory = old XOR Rs. A/R bits add acquire/release (ldeora, ldeorl, ldeoral). |
LSE |
|
31–30size11 29–271 1 1 260 25–240 0 23A0 22R0 211 20–16Rs00000 150 14–120 1 0 11–100 0 9–5Rn00010 4–0Rt00001
Example
ldeor x0, x1, [x2]f820204141 20 20 f8 |
|||
| ldset | Rs, Rt, [Xn] |
Atomic bit-set (OR): Rt = old value, memory = old bit-set Rs. A/R bits add acquire/release (ldseta, ldsetl, ldsetal). |
LSE |
|
31–30size11 29–271 1 1 260 25–240 0 23A0 22R0 211 20–16Rs00000 150 14–120 1 1 11–100 0 9–5Rn00010 4–0Rt00001
Example
ldset x0, x1, [x2]f820304141 30 20 f8 |
|||
| ldsmax | Rs, Rt, [Xn] |
Atomic signed max: Rt = old value, memory = old signed Rs. A/R bits add acquire/release (ldsmaxa, ldsmaxl, ldsmaxal). |
LSE |
|
31–30size11 29–271 1 1 260 25–240 0 23A0 22R0 211 20–16Rs00000 150 14–121 0 0 11–100 0 9–5Rn00010 4–0Rt00001 Example
ldsmax x0, x1, [x2]f820404141 40 20 f8 |
|||
| ldsmin | Rs, Rt, [Xn] |
Atomic signed min: Rt = old value, memory = old signed Rs. A/R bits add acquire/release (ldsmina, ldsminl, ldsminal). |
LSE |
|
31–30size11 29–271 1 1 260 25–240 0 23A0 22R0 211 20–16Rs00000 150 14–121 0 1 11–100 0 9–5Rn00010 4–0Rt00001 Example
ldsmin x0, x1, [x2]f820504141 50 20 f8 |
|||
| ldumax | Rs, Rt, [Xn] |
Atomic unsigned max: Rt = old value, memory = old unsigned Rs. A/R bits add acquire/release (ldumaxa, ldumaxl, ldumaxal). |
LSE |
|
31–30size11 29–271 1 1 260 25–240 0 23A0 22R0 211 20–16Rs00000 150 14–121 1 0 11–100 0 9–5Rn00010 4–0Rt00001 Example
ldumax x0, x1, [x2]f820604141 60 20 f8 |
|||
| ldumin | Rs, Rt, [Xn] |
Atomic unsigned min: Rt = old value, memory = old unsigned Rs. A/R bits add acquire/release (ldumina, lduminl, lduminal). |
LSE |
|
31–30size11 29–271 1 1 260 25–240 0 23A0 22R0 211 20–16Rs00000 150 14–121 1 1 11–100 0 9–5Rn00010 4–0Rt00001 Example
ldumin x0, x1, [x2]f820704141 70 20 f8 |
|||
| swp | Rs, Rt, [Xn] |
Atomic swap: Rt = old value, memory = Rs. | LSE |
|
31–30size11 29–271 1 1 260 25–240 0 23A0 22R0 211 20–16Rs00000 151 14–120 0 0 11–100 0 9–5Rn00010 4–0Rt00001 Ordering variants Example
swp x0, x1, [x2]f820804141 80 20 f8 |
|||
| cas | Rs, Rt, [Xn] |
Compare-and-swap: if memory == Rs, write Rt; Rs gets the old value. | LSE |
|
31–30size11 29–230 0 1 0 0 0 1 220 211 20–16Rs00000 150 14–101 1 1 1 1 9–5Rn00010 4–0Rt00001
Example
cas x0, x1, [x2]c8a07c4141 7c a0 c8 |
|||
| casal | Rs, Rt, [Xn] |
Compare-and-swap with acquire and release ordering. | LSE |
|
31–30size11 29–230 0 1 0 0 0 1 221 211 20–16Rs00000 151 14–101 1 1 1 1 9–5Rn00010 4–0Rt00001 Example
casal x0, x1, [x2]c8e0fc4141 fc e0 c8 |
|||
| System | |||
| svc | #imm16 |
Supervisor call: trap to EL1 (system call). | Base |
|
31–241 1 0 1 0 1 0 0 23–210 0 0 20–5imm160000000000000000 4–00 0 0 0 1 Linux: number in Example
svc #0d400000101 00 00 d4 |
|||
| hvc | #imm16 |
Hypervisor call: trap to EL2. | Base |
|
31–241 1 0 1 0 1 0 0 23–210 0 0 20–5imm160000000000000000 4–00 0 0 1 0 Example
hvc #0d400000202 00 00 d4 |
|||
| smc | #imm16 |
Secure monitor call: trap to EL3. | Base |
|
31–241 1 0 1 0 1 0 0 23–210 0 0 20–5imm160000000000000000 4–00 0 0 1 1 Example
smc #0d400000303 00 00 d4 |
|||
| brk | #imm16 |
Software breakpoint: a debug exception. | Base |
|
31–241 1 0 1 0 1 0 0 23–210 0 1 20–5imm160000000000000000 4–00 0 0 0 0
Example
brk #0d420000000 00 20 d4 |
|||
| hlt | #imm16 |
Halting debug breakpoint (external debugger). | Base |
|
31–241 1 0 1 0 1 0 0 23–210 1 0 20–5imm160000000000000000 4–00 0 0 0 0 Example
hlt #0d440000000 00 40 d4 |
|||
| nop | |
No operation. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 0 0 7–50 0 0 4–01 1 1 1 1 Example
nopd503201f1f 20 03 d5 |
|||
| yield | |
Hint: yield in an SMT core. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 0 0 7–50 0 1 4–01 1 1 1 1 Example
yieldd503203f3f 20 03 d5 |
|||
| wfe | |
Wait for event (low power). | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 0 0 7–50 1 0 4–01 1 1 1 1 Example
wfed503205f5f 20 03 d5 |
|||
| wfi | |
Wait for interrupt (low power). | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 0 0 7–50 1 1 4–01 1 1 1 1 Example
wfid503207f7f 20 03 d5 |
|||
| sev | |
Send event to all cores. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 0 0 7–51 0 0 4–01 1 1 1 1 Example
sevd503209f9f 20 03 d5 |
|||
| sevl | |
Send event locally. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 0 0 7–51 0 1 4–01 1 1 1 1 Example
sevld50320bfbf 20 03 d5 |
|||
| csdb | |
Consumption of speculative data barrier (Spectre mitigation). | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 1 0 7–51 0 0 4–01 1 1 1 1 Example
csdbd503229f9f 22 03 d5 |
|||
| paciasp | |
Sign X30 (LR) using the current SP as modifier. Entry of a protected function. | PAC |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 1 1 7–50 0 1 4–01 1 1 1 1 Encoded as a hint, so it is a NOP on cores without PAC. Example
paciaspd503233f3f 23 03 d5 |
|||
| autiasp | |
Authenticate X30 signed with SP; a bad signature poisons the pointer so the next use faults. | PAC |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 1 1 7–51 0 1 4–01 1 1 1 1 Example
autiaspd50323bfbf 23 03 d5 |
|||
| bti | {c|j|jc} |
Branch target identification landing pad; guards indirect-branch targets. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 1 0 0 7–6x01 50 4–01 1 1 1 1 Example
bti cd503245f5f 24 03 d5 |
|||
| isb | {#imm} |
Instruction synchronization barrier: flush the pipeline so later instructions see prior system changes. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 1 11–8CRm1111 7–51 1 0 4–01 1 1 1 1 Example
isbd5033fdfdf 3f 03 d5 |
|||
| dsb | option |
Data synchronization barrier: wait until prior memory accesses complete. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 1 11–8CRm1111 7–51 0 0 4–01 1 1 1 1 Example
dsb syd5033f9f9f 3f 03 d5 |
|||
| dmb | option |
Data memory barrier: order memory accesses without stalling other work. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 1 11–8CRm1011 7–51 0 1 4–01 1 1 1 1 Example
dmb ishd5033bbfbf 3b 03 d5 |
|||
| sb | |
Speculation barrier: later instructions do not speculatively execute until this completes. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 1 11–80 0 0 0 7–51 1 1 4–01 1 1 1 1 Example
sbd50330ffff 30 03 d5 |
|||
| clrex | {#imm} |
Clear the local exclusive monitor. | Base |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 1 11–8CRm1111 7–50 1 0 4–01 1 1 1 1 Example
clrexd5033f5f5f 3f 03 d5 |
|||
| mrs | Xt, sysreg |
Read a system register into Xt. | Base |
|
31–221 1 0 1 0 1 0 1 0 0 211 201 19o01 18–16op1011 15–12CRn1101 11–8CRm0000 7–5op2010 4–0Rt00000
Example
mrs x0, tpidr_el0d53bd04040 d0 3b d5 |
|||
| msr (reg) | sysreg, Xt |
Write Xt to a system register. | Base |
|
31–221 1 0 1 0 1 0 1 0 0 210 201 19o01 18–16op1011 15–12CRn1101 11–8CRm0000 7–5op2010 4–0Rt00000 Example
msr tpidr_el0, x0d51bd04040 d0 1b d5 |
|||
| msr (imm) | pstatefield, #imm |
Write an immediate to a PSTATE field (e.g. DAIFSet, SPSel, PAN). | Base |
|
31–221 1 0 1 0 1 0 1 0 0 210 20–190 0 18–16op1011 15–120 1 0 0 11–8CRm0010 7–5op2111 4–01 1 1 1 1 Example
msr daifclr, #2d50342ffff 42 03 d5 |
|||
| sys | #op1, Cn, Cm, #op2{, Xt} |
Generic system instruction (the encoding behind DC, IC, AT, TLBI). | Base |
|
31–221 1 0 1 0 1 0 1 0 0 210 20–190 1 18–16op1011 15–12CRn0111 11–8CRm0101 7–5op2001 4–0Rt00000 Example
sys #3, c7, c5, #1, x0d50b752020 75 0b d5 |
|||
| sysl | Xt, #op1, Cn, Cm, #op2 |
Generic system instruction with a result in Xt. | Base |
|
31–221 1 0 1 0 1 0 1 0 0 211 20–190 1 18–16op1011 15–12CRn0111 11–8CRm0101 7–5op2001 4–0Rt00000 Example
sysl x0, #3, c7, c5, #1d52b752020 75 2b d5 |
|||
| ic | ialluis |
Instruction cache maintenance (here: invalidate all to PoU, inner shareable). | Base |
|
31–221 1 0 1 0 1 0 1 0 0 210 20–190 1 18–160 0 0 15–120 1 1 1 11–80 0 0 1 7–50 0 0 4–01 1 1 1 1 Example
ic ialluisd508711f1f 71 08 d5 |
|||
| dc | op, Xt |
Data cache maintenance by address (CIVAC, CVAC, ZVA, ...). | Base |
|
31–221 1 0 1 0 1 0 1 0 0 210 20–190 1 18–16op1011 15–120 1 1 1 11–8CRm1110 7–5op2001 4–0Rt00000
Example
dc civac, x0d50b7e2020 7e 0b d5 |
|||
| at | s1e0r, Xt |
Address translation: run the MMU translation for an address and put the result in PAR_EL1. | Base |
|
31–221 1 0 1 0 1 0 1 0 0 210 20–190 1 18–160 0 0 15–120 1 1 1 11–81 0 0 0 7–50 1 0 4–0Rt00000 Example
at s1e0r, x0d508784040 78 08 d5 |
|||
| tlbi | op{, Xt} |
TLB invalidate (by VA, ASID, all, inner-shareable variants, ...). | Base |
|
31–221 1 0 1 0 1 0 1 0 0 210 20–190 1 18–16op1000 15–121 0 0 0 11–8CRm0011 7–5op2000 4–0Rt11111 Example
tlbi vmalle1isd508831f1f 83 08 d5 |
|||
| dcps1 | {#imm} |
Debug change PE state to EL1. | Base |
|
31–241 1 0 1 0 1 0 0 23–211 0 1 20–5imm160000000000000000 4–00 0 0 0 1 Example
dcps1d4a0000101 00 a0 d4 |
|||
| CRC32 | |||
| crc32b | Wd, Wn, Wm |
CRC32 accumulate over a byte (poly 0x04C11DB7). | CRC |
|
310 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–130 1 0 120 11–100 0 9–5Rn00001 4–0Rd00000 Example
crc32b w0, w1, w21ac2402020 40 c2 1a |
|||
| crc32h | Wd, Wn, Wm |
CRC32 accumulate over a halfword (poly 0x04C11DB7). | CRC |
|
310 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–130 1 0 120 11–100 1 9–5Rn00001 4–0Rd00000 Example
crc32h w0, w1, w21ac2442020 44 c2 1a |
|||
| crc32w | Wd, Wn, Wm |
CRC32 accumulate over a word (poly 0x04C11DB7). | CRC |
|
310 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–130 1 0 120 11–101 0 9–5Rn00001 4–0Rd00000 Example
crc32w w0, w1, w21ac2482020 48 c2 1a |
|||
| crc32cb | Wd, Wn, Wm |
CRC32C accumulate over a byte (poly 0x04C11DB7, Castagnoli). | CRC |
|
310 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–130 1 0 121 11–100 0 9–5Rn00001 4–0Rd00000 Example
crc32cb w0, w1, w21ac2502020 50 c2 1a |
|||
| crc32ch | Wd, Wn, Wm |
CRC32C accumulate over a halfword (poly 0x04C11DB7, Castagnoli). | CRC |
|
310 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–130 1 0 121 11–100 1 9–5Rn00001 4–0Rd00000 Example
crc32ch w0, w1, w21ac2542020 54 c2 1a |
|||
| crc32cw | Wd, Wn, Wm |
CRC32C accumulate over a word (poly 0x04C11DB7, Castagnoli). | CRC |
|
310 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–130 1 0 121 11–101 0 9–5Rn00001 4–0Rd00000 Example
crc32cw w0, w1, w21ac2582020 58 c2 1a |
|||
| crc32x | Wd, Wn, Xm |
CRC32 accumulate over a doubleword. | CRC |
|
311 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–130 1 0 120 11–101 1 9–5Rn00001 4–0Rd00000 Example
crc32x w0, w1, x29ac24c2020 4c c2 9a |
|||
| crc32cx | Wd, Wn, Xm |
CRC32C (Castagnoli) over a doubleword. | CRC |
|
311 300 290 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–130 1 0 121 11–101 1 9–5Rn00001 4–0Rd00000 Example
crc32cx w0, w1, x29ac25c2020 5c c2 9a |
|||
| Cryptography | |||
| aese | Vd.16B, Vn.16B |
One AES encryption round: SubBytes + ShiftRows + AddRoundKey on the state. | AES |
|
31–240 1 0 0 1 1 1 0 23–220 0 21–171 0 1 0 0 16–120 0 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
aese v0.16b, v1.16b4e28482020 48 28 4e |
|||
| aesd | Vd.16B, Vn.16B |
One AES decryption round. | AES |
|
31–240 1 0 0 1 1 1 0 23–220 0 21–171 0 1 0 0 16–120 0 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
aesd v0.16b, v1.16b4e28582020 58 28 4e |
|||
| aesmc | Vd.16B, Vn.16B |
AES MixColumns. | AES |
|
31–240 1 0 0 1 1 1 0 23–220 0 21–171 0 1 0 0 16–120 0 1 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
aesmc v0.16b, v1.16b4e28682020 68 28 4e |
|||
| aesimc | Vd.16B, Vn.16B |
AES InverseMixColumns. | AES |
|
31–240 1 0 0 1 1 1 0 23–220 0 21–171 0 1 0 0 16–120 0 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
aesimc v0.16b, v1.16b4e28782020 78 28 4e |
|||
| sha1c | Qd, Sn, Vm.4S |
SHA1 hash update, choose function. | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 210 20–16Rm00010 15–130 0 0 120 11–100 0 9–5Rn00001 4–0Rd00000 Example
sha1c q0, s1, v2.4s5e02002020 00 02 5e |
|||
| sha1h | Sd, Sn |
SHA1 fixed rotate (ROL 30). | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 21–171 0 1 0 0 16–120 0 0 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
sha1h s0, s15e28082020 08 28 5e |
|||
| sha256h | Qd, Qn, Vm.4S |
SHA256 hash update (part 1). | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 210 20–16Rm00010 15–120 1 0 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
sha256h q0, q1, v2.4s5e02402020 40 02 5e |
|||
| sha256su0 | Vd.4S, Vn.4S |
SHA256 schedule update 0. | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 21–171 0 1 0 0 16–120 0 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
sha256su0 v0.4s, v1.4s5e28282020 28 28 5e |
|||
| sha1p | Qd, Sn, Vm.4S |
SHA1 hash update (parity choice). | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 210 20–16Rm00010 15–130 0 0 121 11–100 0 9–5Rn00001 4–0Rd00000 Example
sha1p q0, s1, v2.4s5e02102020 10 02 5e |
|||
| sha1m | Qd, Sn, Vm.4S |
SHA1 hash update (majority choice). | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 210 20–16Rm00010 15–130 0 1 120 11–100 0 9–5Rn00001 4–0Rd00000 Example
sha1m q0, s1, v2.4s5e02202020 20 02 5e |
|||
| sha1su0 | Vd.4S, Vn.4S, Vm.4S |
SHA1 schedule update 0. | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 210 20–16Rm00010 15–130 0 1 121 11–100 0 9–5Rn00001 4–0Rd00000 Example
sha1su0 v0.4s, v1.4s, v2.4s5e02302020 30 02 5e |
|||
| sha1su1 | Vd.4S, Vn.4S |
SHA1 schedule update 1. | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 21–171 0 1 0 0 16–120 0 0 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
sha1su1 v0.4s, v1.4s5e28182020 18 28 5e |
|||
| sha256h2 | Qd, Qn, Vm.4S |
SHA256 hash update (part 2). | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 210 20–16Rm00010 15–120 1 0 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
sha256h2 q0, q1, v2.4s5e02502020 50 02 5e |
|||
| sha256su1 | Vd.4S, Vn.4S, Vm.4S |
SHA256 schedule update 1. | SHA |
|
31–240 1 0 1 1 1 1 0 23–220 0 210 20–16Rm00010 15–120 1 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
sha256su1 v0.4s, v1.4s, v2.4s5e02602020 60 02 5e |
|||
| pmull (poly) | Vd.1Q, Vn.1D, Vm.1D |
Polynomial multiply long of 64-bit halves (GHASH / GCM). | AES |
|
310 300 290 28–240 1 1 1 0 23–221 1 211 20–16Rm00010 15–121 1 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
pmull v0.1q, v1.1d, v2.1d0ee2e02020 e0 e2 0e |
|||
| eor3 | Vd.16B, Vn.16B, Vm.16B, Va.16B |
Three-way XOR: Vd = Vn ^ Vm ^ Va. | SHA3 |
|
31–241 1 0 0 1 1 1 0 23–220 0 210 20–16Rm00010 150 14–10Ra00011 9–5Rn00001 4–0Rd00000 Example
eor3 v0.16b, v1.16b, v2.16b, v3.16bce020c2020 0c 02 ce |
|||
| bcax | Vd.16B, Vn.16B, Vm.16B, Va.16B |
Bit-clear and XOR: Vd = Vn ^ (Vm & ~Va). | SHA3 |
|
31–241 1 0 0 1 1 1 0 23–220 0 211 20–16Rm00010 150 14–10Ra00011 9–5Rn00001 4–0Rd00000 Example
bcax v0.16b, v1.16b, v2.16b, v3.16bce220c2020 0c 22 ce |
|||
| rax1 | Vd.2D, Vn.2D, Vm.2D |
Rotate each 64-bit lane of Vm left by 1 and XOR with Vn. | SHA3 |
|
31–241 1 0 0 1 1 1 0 23–220 1 211 20–16Rm00010 15–101 0 0 0 1 1 9–5Rn00001 4–0Rd00000 Example
rax1 v0.2d, v1.2d, v2.2dce628c2020 8c 62 ce |
|||
| xar | Vd.2D, Vn.2D, Vm.2D, #imm6 |
XOR then rotate right each 64-bit lane by an immediate. | SHA3 |
|
31–241 1 0 0 1 1 1 0 23–211 0 0 20–16Rm00010 15–10imm6000111 9–5Rn00001 4–0Rd00000 Example
xar v0.2d, v1.2d, v2.2d, #7ce821c2020 1c 82 ce |
|||
| sm4e | Vd.4S, Vn.4S |
SM4 encryption round. | SM4 |
|
31–241 1 0 0 1 1 1 0 23–221 1 21–170 0 0 0 0 160 15–111 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
sm4e v0.4s, v1.4scec0842020 84 c0 ce |
|||
| sm3partw1 | Vd.4S, Vn.4S, Vm.4S |
SM3 message schedule, part 1. | SM3 |
|
31–241 1 0 0 1 1 1 0 23–210 1 1 20–16Rm00010 15–101 1 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
sm3partw1 v0.4s, v1.4s, v2.4sce62c02020 c0 62 ce |
|||
| Memory tagging (MTE) | |||
| irg | Xd, Xn{, Xm} |
Insert a random logical tag into the top bits of the address in Xn. | MTE |
|
311 30–290 0 28–211 1 0 1 0 1 1 0 20–16Rm11111 15–100 0 0 1 0 0 9–5Rn00001 4–0Rd00000 Example
irg x0, x19adf102020 10 df 9a |
|||
| addg | Xd, Xn, #imm, #tag |
Add an unscaled immediate and adjust the logical tag. | MTE |
|
311 30–290 0 28–231 0 0 0 1 1 220 21–16uimm6000001 15–140 0 13–10uimm40001 9–5Rn00001 4–0Rd00000 Example
addg x0, x1, #16, #19181042020 04 81 91 |
|||
| stg | Xt, [Xn, #off] |
Store the allocation tag for the 16-byte granule at the address. | MTE |
|
31–241 1 0 1 1 0 0 1 23–220 0 211 20–12imm9000000000 11–101 0 9–5Rn00001 4–0Rt00000 Example
stg x0, [x1]d920082020 08 20 d9 |
|||
| ldg | Xt, [Xn, #off] |
Load the allocation tag of a granule into the tag field of Xt. | MTE |
|
31–241 1 0 1 1 0 0 1 23–220 1 211 20–12imm9000000000 11–100 0 9–5Rn00001 4–0Rt00000 Example
ldg x0, [x1]d960002020 00 60 d9 |
|||
| Floating point | |||
| fmov (reg) | Fd, Fn |
Copy one FP register to another. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–170 0 0 0 16–150 0 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fmov d0, d11e60402020 40 60 1e |
|||
| fmov (imm) | Fd, #imm |
Load a small FP constant (8-bit encoded). | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–13imm801110000 12–101 0 0 9–50 0 0 0 0 4–0Rd00000 Example
fmov d0, #1.01e6e100000 10 6e 1e |
|||
| fmov (to gpr) | Rd, Fn |
Copy the raw bits of an FP register to a general register. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–19rmode00 18–161 1 0 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fmov x0, d19e66002020 00 66 9e |
|||
| fmov (from gpr) | Fd, Rn |
Copy the bits of a general register into an FP register. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–19rmode00 18–161 1 1 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fmov d0, x19e67002020 00 67 9e |
|||
| fadd | Fd, Fn, Fm |
Sum of two FP registers. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–130 0 1 120 11–101 0 9–5Rn00001 4–0Rd00000 Example
fadd d0, d1, d21e62282020 28 62 1e |
|||
| fsub | Fd, Fn, Fm |
Difference of two FP registers. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–130 0 1 121 11–101 0 9–5Rn00001 4–0Rd00000 Example
fsub d0, d1, d21e62382020 38 62 1e |
|||
| fmul | Fd, Fn, Fm |
Product of two FP registers. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–130 0 0 120 11–101 0 9–5Rn00001 4–0Rd00000 Example
fmul d0, d1, d21e62082020 08 62 1e |
|||
| fdiv | Fd, Fn, Fm |
Quotient of two FP registers. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–130 0 0 121 11–101 0 9–5Rn00001 4–0Rd00000 Example
fdiv d0, d1, d21e62182020 18 62 1e |
|||
| fnmul | Fd, Fn, Fm |
Negated product: Fd = -(Fn × Fm). | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–131 0 0 120 11–101 0 9–5Rn00001 4–0Rd00000 Example
fnmul d0, d1, d21e62882020 88 62 1e |
|||
| fabs | Fd, Fn |
Absolute value. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–170 0 0 0 16–150 1 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fabs d0, d11e60c02020 c0 60 1e |
|||
| fneg | Fd, Fn |
Negate. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–170 0 0 0 16–151 0 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fneg d0, d11e61402020 40 61 1e |
|||
| fsqrt | Fd, Fn |
Square root. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–170 0 0 0 16–151 1 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fsqrt d0, d11e61c02020 c0 61 1e |
|||
| fmadd | Fd, Fn, Fm, Fa |
Fused multiply-add: Fd = Fa + Fn × Fm (single rounding). | FP |
|
310 300 290 28–241 1 1 1 1 23–22ftype01 210 20–16Rm00010 150 14–10Ra00011 9–5Rn00001 4–0Rd00000 Example
fmadd d0, d1, d2, d31f420c2020 0c 42 1f |
|||
| fmsub | Fd, Fn, Fm, Fa |
Fused multiply-subtract: Fd = Fa - Fn × Fm. | FP |
|
310 300 290 28–241 1 1 1 1 23–22ftype01 210 20–16Rm00010 151 14–10Ra00011 9–5Rn00001 4–0Rd00000 Example
fmsub d0, d1, d2, d31f428c2020 8c 42 1f |
|||
| fnmadd | Fd, Fn, Fm, Fa |
Fd = -Fa - Fn × Fm. | FP |
|
310 300 290 28–241 1 1 1 1 23–22ftype01 211 20–16Rm00010 150 14–10Ra00011 9–5Rn00001 4–0Rd00000 Example
fnmadd d0, d1, d2, d31f620c2020 0c 62 1f |
|||
| fcmp | Fn, Fm |
Compare two FP registers and set NZCV. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00001 15–140 0 13–101 0 0 0 9–5Rn00000 40 3–00 0 0 0
Example
fcmp d0, d11e61200000 20 61 1e |
|||
| fccmp | Fn, Fm, #nzcv, cond |
Conditional FP compare: if cond holds, set flags from the compare; otherwise set #nzcv. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00001 15–12cond0001 11–100 1 9–5Rn00000 40 3–0nzcv0000 Example
fccmp d0, d1, #0, ne1e61140000 14 61 1e |
|||
| fcsel | Fd, Fn, Fm, cond |
Fd = cond ? Fn : Fm. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–12cond0001 11–101 1 9–5Rn00001 4–0Rd00000 Example
fcsel d0, d1, d2, ne1e621c2020 1c 62 1e |
|||
| fmax | Fd, Fn, Fm |
Maximum (the nm forms follow IEEE NaN rules). |
FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–120 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fmax d0, d1, d21e62482020 48 62 1e |
|||
| fmin | Fd, Fn, Fm |
Minimum (the nm forms follow IEEE NaN rules). |
FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–120 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fmin d0, d1, d21e62582020 58 62 1e |
|||
| fmaxnm | Fd, Fn, Fm |
Maximum (the nm forms follow IEEE NaN rules). |
FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–120 1 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fmaxnm d0, d1, d21e62682020 68 62 1e |
|||
| fminnm | Fd, Fn, Fm |
Minimum (the nm forms follow IEEE NaN rules). |
FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00010 15–120 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fminnm d0, d1, d21e62782020 78 62 1e |
|||
| fcvt | Fd, Fn |
Convert between FP precisions (opc picks the destination type). | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–170 0 0 1 16–15opc00 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvt s0, d11e62402020 40 62 1e |
|||
| scvtf | Fd, Rn |
Convert a signed integer register to FP. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–190 0 18–160 1 0 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
scvtf d0, x19e62002020 00 62 9e |
|||
| ucvtf | Fd, Rn |
Convert an unsigned integer register to FP. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–190 0 18–160 1 1 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
ucvtf d0, x19e63002020 00 63 9e |
|||
| fcvtzs | Rd, Fn |
Convert FP to a signed integer, rounding toward zero. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–191 1 18–160 0 0 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtzs x0, d19e78002020 00 78 9e |
|||
| fcvtzu | Rd, Fn |
Convert FP to an unsigned integer, rounding toward zero. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–191 1 18–160 0 1 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtzu x0, d19e79002020 00 79 9e |
|||
| frintm | Fd, Fn |
Round to an integral FP value, toward minus infinity (floor). | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–180 0 1 17–150 1 0 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Other modes: Example
frintm d0, d11e65402020 40 65 1e |
|||
| fcvtns | Rd, Fn |
Convert FP to integer, rounding nearest, ties to even. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–190 0 18–160 0 0 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtns x0, d19e60002020 00 60 9e |
|||
| fcvtnu | Rd, Fn |
Convert FP to integer, rounding nearest, ties to even (unsigned). | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–190 0 18–160 0 1 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtnu x0, d19e61002020 00 61 9e |
|||
| fcvtps | Rd, Fn |
Convert FP to integer, rounding toward +inf. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–190 1 18–160 0 0 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtps x0, d19e68002020 00 68 9e |
|||
| fcvtpu | Rd, Fn |
Convert FP to integer, rounding toward +inf (unsigned). | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–190 1 18–160 0 1 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtpu x0, d19e69002020 00 69 9e |
|||
| fcvtms | Rd, Fn |
Convert FP to integer, rounding toward -inf. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–191 0 18–160 0 0 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtms x0, d19e70002020 00 70 9e |
|||
| fcvtmu | Rd, Fn |
Convert FP to integer, rounding toward -inf (unsigned). | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–191 0 18–160 0 1 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtmu x0, d19e71002020 00 71 9e |
|||
| fcvtas | Rd, Fn |
Convert FP to integer, rounding nearest, ties away. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–190 0 18–161 0 0 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtas x0, d19e64002020 00 64 9e |
|||
| fcvtau | Rd, Fn |
Convert FP to integer, rounding nearest, ties away (unsigned). | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 211 20–190 0 18–161 0 1 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fcvtau x0, d19e65002020 00 65 9e |
|||
| fcvtzs (fixed) | Rd, Fn, #fbits |
Convert FP to a fixed-point integer with #fbits fractional bits. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 210 20–191 1 18–160 0 0 15–10scale111000 9–5Rn00001 4–0Rd00000 Example
fcvtzs x0, d1, #89e58e02020 e0 58 9e |
|||
| fcvtzu (fixed) | Rd, Fn, #fbits |
Convert FP to an unsigned fixed-point integer. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 210 20–191 1 18–160 0 1 15–10scale111000 9–5Rn00001 4–0Rd00000 Example
fcvtzu x0, d1, #89e59e02020 e0 59 9e |
|||
| scvtf (fixed) | Fd, Rn, #fbits |
Convert a signed fixed-point integer to FP. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 210 20–190 0 18–160 1 0 15–10scale111000 9–5Rn00001 4–0Rd00000 Example
scvtf d0, x1, #89e42e02020 e0 42 9e |
|||
| ucvtf (fixed) | Fd, Rn, #fbits |
Convert an unsigned fixed-point integer to FP. | FP |
|
31sf1 300 290 28–241 1 1 1 0 23–22ftype01 210 20–190 0 18–160 1 1 15–10scale111000 9–5Rn00001 4–0Rd00000 Example
ucvtf d0, x1, #89e43e02020 e0 43 9e |
|||
| fjcvtzs | Wd, Dn |
JavaScript convert double to signed 32-bit, rounding toward zero (sets Z if exact). | FP |
|
310 300 290 28–241 1 1 1 0 23–220 1 211 20–191 1 18–161 1 0 15–100 0 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
fjcvtzs w0, d11e7e002020 00 7e 1e |
|||
| fcmpe | Fn, Fm |
Compare and set NZCV, raising Invalid Operation on any NaN (signalling compare). | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00001 15–140 0 13–101 0 0 0 9–5Rn00000 41 3–00 0 0 0 Example
fcmpe d0, d11e61201010 20 61 1e |
|||
| fccmpe | Fn, Fm, #nzcv, cond |
Conditional signalling compare. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–16Rm00001 15–12cond0001 11–100 1 9–5Rn00000 41 3–0nzcv0000 Example
fccmpe d0, d1, #0, ne1e61141010 14 61 1e |
|||
| frintn | Fd, Fn |
Round to an integral FP value, nearest, ties to even. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–180 0 1 17–150 0 0 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
frintn d0, d11e64402020 40 64 1e |
|||
| frintp | Fd, Fn |
Round to an integral FP value, toward +inf (ceil). | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–180 0 1 17–150 0 1 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
frintp d0, d11e64c02020 c0 64 1e |
|||
| frintm | Fd, Fn |
Round to an integral FP value, toward -inf (floor). | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–180 0 1 17–150 1 0 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
frintm d0, d11e65402020 40 65 1e |
|||
| frintz | Fd, Fn |
Round to an integral FP value, toward zero (trunc). | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–180 0 1 17–150 1 1 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
frintz d0, d11e65c02020 c0 65 1e |
|||
| frinta | Fd, Fn |
Round to an integral FP value, nearest, ties away. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–180 0 1 17–151 0 0 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
frinta d0, d11e66402020 40 66 1e |
|||
| frintx | Fd, Fn |
Round to an integral FP value, current mode, raise Inexact. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–180 0 1 17–151 1 0 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
frintx d0, d11e67402020 40 67 1e |
|||
| frinti | Fd, Fn |
Round to an integral FP value, current mode. | FP |
|
310 300 290 28–241 1 1 1 0 23–22ftype01 211 20–180 0 1 17–151 1 1 14–101 0 0 0 0 9–5Rn00001 4–0Rd00000 Example
frinti d0, d11e67c02020 c0 67 1e |
|||
| fmaxp (scalar) | Fd, Vn.2S |
Pairwise maximum of a two-element vector into a scalar. | FP |
|
310 301 291 28–241 1 1 1 0 230 22sz0 21–171 1 0 0 0 16–120 1 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fmaxp s0, v1.2s7e30f82020 f8 30 7e |
|||
| SIMD (Advanced SIMD) | |||
| ld1 (mult) | {Vt.T}, [Xn] |
Load one to four vectors from contiguous memory. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 221 21–160 0 0 0 0 0 15–12opcode0111 11–10size00 9–5Rn00001 4–0Rt00000 Example
ld1 {v0.16b}, [x1]4c40702020 70 40 4c |
|||
| st1 (mult) | {Vt.T}, [Xn] |
Store one to four vectors to contiguous memory. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 220 21–160 0 0 0 0 0 15–12opcode0111 11–10size00 9–5Rn00001 4–0Rt00000 Example
st1 {v0.16b}, [x1]4c00702020 70 00 4c |
|||
| ldr (q) | Qt, [Xn, #off] |
Load a 128-bit vector register. | SIMD |
|
31–300 0 29–271 1 1 261 25–240 1 23–221 1 21–10imm12000000000001 9–5Rn00001 4–0Rt00000 Example
ldr q0, [x1, #16]3dc0042020 04 c0 3d |
|||
| dup (elem) | Vd.T, Vn.Ts[i] |
Duplicate one element across all lanes. | SIMD |
|
310 30Q1 290 28–210 1 1 1 0 0 0 0 20–16imm501100 15–100 0 0 0 0 1 9–5Rn00001 4–0Rd00000 Example
dup v0.4s, v1.s[1]4e0c042020 04 0c 4e |
|||
| dup (gpr) | Vd.T, Rn |
Duplicate a general register into every lane. | SIMD |
|
310 30Q1 290 28–210 1 1 1 0 0 0 0 20–16imm500100 15–100 0 0 0 1 1 9–5Rn00001 4–0Rd00000 Example
dup v0.4s, w14e040c2020 0c 04 4e |
|||
| ins (elem) | Vd.Ts[i], Vn.Ts[j] |
Copy one element to a lane of Vd. | SIMD |
|
310 301 291 28–210 1 1 1 0 0 0 0 20–16imm500100 150 14–11imm40100 101 9–5Rn00001 4–0Rd00000 Example
ins v0.s[0], v1.s[1]6e04242020 24 04 6e |
|||
| ins (gpr) | Vd.Ts[i], Rn |
Insert a general register into a lane. | SIMD |
|
310 301 290 28–210 1 1 1 0 0 0 0 20–16imm500100 15–100 0 0 1 1 1 9–5Rn00001 4–0Rd00000 Example
ins v0.s[0], w14e041c2020 1c 04 4e |
|||
| umov | Rd, Vn.Ts[i] |
Move a vector element to a general register (zero-extended). | SIMD |
|
310 30Q0 290 28–210 1 1 1 0 0 0 0 20–16imm510100 15–100 0 1 1 1 1 9–5Rn00001 4–0Rd00000 Example
umov w0, v1.s[2]0e143c2020 3c 14 0e |
|||
| smov | Rd, Vn.Ts[i] |
Move a vector element to a general register, sign-extended. | SIMD |
|
310 30Q1 290 28–210 1 1 1 0 0 0 0 20–16imm501010 15–100 0 1 0 1 1 9–5Rn00001 4–0Rd00000 Example
smov x0, v1.h[2]4e0a2c2020 2c 0a 4e |
|||
| movi | Vd.T, #imm |
Set every lane to an encoded immediate. | SIMD |
|
310 30Q1 290 28–190 1 1 1 1 0 0 0 0 0 18–16abc111 15–12cmode1110 11–100 1 9–5defgh11111 4–0Rd00000 Example
movi v0.16b, #0xff4f07e7e0e0 e7 07 4f |
|||
| add (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise integer add. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–101 0 0 0 0 1 9–5Rn00001 4–0Rd00000 Example
add v0.4s, v1.4s, v2.4s4ea2842020 84 a2 4e |
|||
| sub (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise integer subtract. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–101 0 0 0 0 1 9–5Rn00001 4–0Rd00000 Example
sub v0.4s, v1.4s, v2.4s6ea2842020 84 a2 6e |
|||
| mul (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise integer multiply. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–101 0 0 1 1 1 9–5Rn00001 4–0Rd00000 Example
mul v0.4s, v1.4s, v2.4s4ea29c2020 9c a2 4e |
|||
| cmeq (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise compare equal (all-ones or zero per lane). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–101 0 0 0 1 1 9–5Rn00001 4–0Rd00000 Example
cmeq v0.4s, v1.4s, v2.4s6ea28c2020 8c a2 6e |
|||
| fadd (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP add. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 22sz0 211 20–16Rm00010 15–101 1 0 1 0 1 9–5Rn00001 4–0Rd00000 Example
fadd v0.4s, v1.4s, v2.4s4e22d42020 d4 22 4e |
|||
| fmul (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP multiply. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 22sz0 211 20–16Rm00010 15–101 1 0 1 1 1 9–5Rn00001 4–0Rd00000 Example
fmul v0.4s, v1.4s, v2.4s6e22dc2020 dc 22 6e |
|||
| and (vec) | Vd.T, Vn.T, Vm.T |
Bitwise AND of two vectors. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–220 0 211 20–16Rm00010 15–100 0 0 1 1 1 9–5Rn00001 4–0Rd00000 Example
and v0.16b, v1.16b, v2.16b4e221c2020 1c 22 4e |
|||
| eor (vec) | Vd.T, Vn.T, Vm.T |
Bitwise XOR of two vectors. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–220 0 211 20–16Rm00010 15–100 0 0 1 1 1 9–5Rn00001 4–0Rd00000 Example
eor v0.16b, v1.16b, v2.16b6e221c2020 1c 22 6e |
|||
| cnt | Vd.T, Vn.T |
Count set bits in each byte lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size00 21–161 0 0 0 0 0 15–100 1 0 1 1 0 9–5Rn00001 4–0Rd00000 Example
cnt v0.16b, v1.16b4e20582020 58 20 4e |
|||
| addv | Vd, Vn.T |
Horizontal add: sum all lanes into one scalar. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 1 0 0 0 16–111 1 0 1 1 1 100 9–5Rn00001 4–0Rd00000 Example
addv s0, v1.4s4eb1b82020 b8 b1 4e |
|||
| tbl | Vd.T, {Vn.16B}, Vm.T |
Table lookup: index a register-table of bytes with Vm, 0 for out-of-range. | SIMD |
|
310 30Q1 29–240 0 1 1 1 0 23–220 0 210 20–16Rm00010 150 14–130 0 120 11–100 0 9–5Rn00001 4–0Rd00000 Example
tbl v0.16b, {v1.16b}, v2.16b4e02002020 00 02 4e |
|||
| ext | Vd.T, Vn.T, Vm.T, #idx |
Extract a byte-aligned window spanning Vn:Vm. | SIMD |
|
310 30Q1 29–241 0 1 1 1 0 23–220 0 210 20–16Rm00010 150 14–11imm40100 100 9–5Rn00001 4–0Rd00000 Example
ext v0.16b, v1.16b, v2.16b, #46e02202020 20 02 6e |
|||
| zip1 | Vd.T, Vn.T, Vm.T |
Interleave the low halves of two vectors. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 150 14–120 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
zip1 v0.4s, v1.4s, v2.4s4e82382020 38 82 4e |
|||
| uzp1 | Vd.T, Vn.T, Vm.T |
Deinterleave, taking the even-indexed elements. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 150 14–120 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
uzp1 v0.4s, v1.4s, v2.4s4e82182020 18 82 4e |
|||
| trn1 | Vd.T, Vn.T, Vm.T |
Transpose, taking the even-indexed elements. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 150 14–120 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
trn1 v0.4s, v1.4s, v2.4s4e82282020 28 82 4e |
|||
| ushr | Vd.T, Vn.T, #sh |
Lane-wise unsigned shift right by an immediate. | SIMD |
|
310 30Q1 291 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–100 0 0 0 0 1 9–5Rn00001 4–0Rd00000 Example
ushr v0.4s, v1.4s, #36f3d042020 04 3d 6f |
|||
| shl | Vd.T, Vn.T, #sh |
Lane-wise shift left by an immediate. | SIMD |
|
310 30Q1 290 28–230 1 1 1 1 0 22–19immh0100 18–16immb011 15–100 1 0 1 0 1 9–5Rn00001 4–0Rd00000 Example
shl v0.4s, v1.4s, #34f23542020 54 23 4f |
|||
| xtn | Vd.Tb, Vn.Ta |
Narrow each lane to half width (take the low part). | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size01 21–161 0 0 0 0 1 15–100 0 1 0 1 0 9–5Rn00001 4–0Rd00000 Example
xtn v0.4h, v1.4s0e61282020 28 61 0e |
|||
| Pointer authentication | |||
| pacia | Xd, Xn |
Sign Xd (an instruction pointer) with key A, using Xn as modifier. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 0 12–100 0 0 9–5Rn00001 4–0Rd00000
Example
pacia x0, x1dac1002020 00 c1 da |
|||
| pacib | Xd, Xn |
Sign an instruction pointer with key B. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 0 12–100 0 1 9–5Rn00001 4–0Rd00000 Example
pacib x0, x1dac1042020 04 c1 da |
|||
| pacda | Xd, Xn |
Sign a data pointer with key A. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 0 12–100 1 0 9–5Rn00001 4–0Rd00000 Example
pacda x0, x1dac1082020 08 c1 da |
|||
| pacdb | Xd, Xn |
Sign a data pointer with key B. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 0 12–100 1 1 9–5Rn00001 4–0Rd00000 Example
pacdb x0, x1dac10c2020 0c c1 da |
|||
| autia | Xd, Xn |
Authenticate an instruction pointer signed with key A; a bad PAC poisons the pointer. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 0 12–101 0 0 9–5Rn00001 4–0Rd00000 Example
autia x0, x1dac1102020 10 c1 da |
|||
| autib | Xd, Xn |
Authenticate an instruction pointer signed with key B. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 0 12–101 0 1 9–5Rn00001 4–0Rd00000 Example
autib x0, x1dac1142020 14 c1 da |
|||
| autda | Xd, Xn |
Authenticate a data pointer signed with key A. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 0 12–101 1 0 9–5Rn00001 4–0Rd00000 Example
autda x0, x1dac1182020 18 c1 da |
|||
| autdb | Xd, Xn |
Authenticate a data pointer signed with key B. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 0 12–101 1 1 9–5Rn00001 4–0Rd00000 Example
autdb x0, x1dac11c2020 1c c1 da |
|||
| paciza | Xd |
Sign Xd with key A, modifier zero. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 1 12–100 0 0 9–51 1 1 1 1 4–0Rd00000 Example
paciza x0dac123e0e0 23 c1 da |
|||
| autiza | Xd |
Authenticate Xd (key A, modifier zero). | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–130 1 12–101 0 0 9–51 1 1 1 1 4–0Rd00000 Example
autiza x0dac133e0e0 33 c1 da |
|||
| xpaci | Xd |
Strip the PAC from an instruction pointer without checking it. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–101 0 0 0 0 9–51 1 1 1 1 4–0Rd00000 Example
xpaci x0dac143e0e0 43 c1 da |
|||
| xpacd | Xd |
Strip the PAC from a data pointer. | PAC |
|
311 301 290 28–211 1 0 1 0 1 1 0 20–160 0 0 0 1 150 14–101 0 0 0 1 9–51 1 1 1 1 4–0Rd00000 Example
xpacd x0dac147e0e0 47 c1 da |
|||
| pacga | Xd, Xn, Xm |
Generic authentication code of Xn with modifier Xm, into the top 32 bits of Xd. | PAC |
|
311 30–290 0 28–211 1 0 1 0 1 1 0 20–16Rm00010 15–100 0 1 1 0 0 9–5Rn00001 4–0Rd00000 Example
pacga x0, x1, x29ac2302020 30 c2 9a |
|||
| pacibsp | |
Sign LR with key B and SP as modifier (hint-space, NOP on older cores). | PAC |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 1 1 7–50 1 1 4–01 1 1 1 1 Example
pacibspd503237f7f 23 03 d5 |
|||
| autibsp | |
Authenticate LR signed with key B and SP. | PAC |
|
31–241 1 0 1 0 1 0 1 23–120 0 0 0 0 0 1 1 0 0 1 0 11–80 0 1 1 7–51 1 1 4–01 1 1 1 1 Example
autibspd50323ffff 23 03 d5 |
|||
| SIMD three-same (integer) | |||
| shadd | Vd.T, Vn.T, Vm.T |
Signed halving add: (a+b)>>1. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
shadd v0.4s, v1.4s, v2.4s4ea2042020 04 a2 4e |
|||
| uhadd | Vd.T, Vn.T, Vm.T |
Unsigned halving add. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
uhadd v0.4s, v1.4s, v2.4s6ea2042020 04 a2 6e |
|||
| sqadd | Vd.T, Vn.T, Vm.T |
Signed saturating add. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
sqadd v0.4s, v1.4s, v2.4s4ea20c2020 0c a2 4e |
|||
| uqadd | Vd.T, Vn.T, Vm.T |
Unsigned saturating add. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
uqadd v0.4s, v1.4s, v2.4s6ea20c2020 0c a2 6e |
|||
| srhadd | Vd.T, Vn.T, Vm.T |
Signed rounding halving add. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
srhadd v0.4s, v1.4s, v2.4s4ea2142020 14 a2 4e |
|||
| urhadd | Vd.T, Vn.T, Vm.T |
Unsigned rounding halving add. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
urhadd v0.4s, v1.4s, v2.4s6ea2142020 14 a2 6e |
|||
| shsub | Vd.T, Vn.T, Vm.T |
Signed halving subtract. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
shsub v0.4s, v1.4s, v2.4s4ea2242020 24 a2 4e |
|||
| uhsub | Vd.T, Vn.T, Vm.T |
Unsigned halving subtract. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
uhsub v0.4s, v1.4s, v2.4s6ea2242020 24 a2 6e |
|||
| sqsub | Vd.T, Vn.T, Vm.T |
Signed saturating subtract. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 1 0 1 101 9–5Rn00001 4–0Rd00000 Example
sqsub v0.4s, v1.4s, v2.4s4ea22c2020 2c a2 4e |
|||
| uqsub | Vd.T, Vn.T, Vm.T |
Unsigned saturating subtract. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 1 0 1 101 9–5Rn00001 4–0Rd00000 Example
uqsub v0.4s, v1.4s, v2.4s6ea22c2020 2c a2 6e |
|||
| cmgt | Vd.T, Vn.T, Vm.T |
Compare greater than (signed), per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
cmgt v0.4s, v1.4s, v2.4s4ea2342020 34 a2 4e |
|||
| cmhi | Vd.T, Vn.T, Vm.T |
Compare higher (unsigned). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
cmhi v0.4s, v1.4s, v2.4s6ea2342020 34 a2 6e |
|||
| cmge | Vd.T, Vn.T, Vm.T |
Compare greater than or equal (signed). | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
cmge v0.4s, v1.4s, v2.4s4ea23c2020 3c a2 4e |
|||
| cmhs | Vd.T, Vn.T, Vm.T |
Compare higher or same (unsigned). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 0 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
cmhs v0.4s, v1.4s, v2.4s6ea23c2020 3c a2 6e |
|||
| sshl | Vd.T, Vn.T, Vm.T |
Signed shift left by vector (negative = right). | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
sshl v0.4s, v1.4s, v2.4s4ea2442020 44 a2 4e |
|||
| ushl | Vd.T, Vn.T, Vm.T |
Unsigned shift left by vector. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
ushl v0.4s, v1.4s, v2.4s6ea2442020 44 a2 6e |
|||
| sqshl | Vd.T, Vn.T, Vm.T |
Signed saturating shift left. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
sqshl v0.4s, v1.4s, v2.4s4ea24c2020 4c a2 4e |
|||
| uqshl | Vd.T, Vn.T, Vm.T |
Unsigned saturating shift left. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
uqshl v0.4s, v1.4s, v2.4s6ea24c2020 4c a2 6e |
|||
| srshl | Vd.T, Vn.T, Vm.T |
Signed rounding shift left. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
srshl v0.4s, v1.4s, v2.4s4ea2542020 54 a2 4e |
|||
| urshl | Vd.T, Vn.T, Vm.T |
Unsigned rounding shift left. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
urshl v0.4s, v1.4s, v2.4s6ea2542020 54 a2 6e |
|||
| sqrshl | Vd.T, Vn.T, Vm.T |
Signed saturating rounding shift left. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
sqrshl v0.4s, v1.4s, v2.4s4ea25c2020 5c a2 4e |
|||
| uqrshl | Vd.T, Vn.T, Vm.T |
Unsigned saturating rounding shift left. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
uqrshl v0.4s, v1.4s, v2.4s6ea25c2020 5c a2 6e |
|||
| smax | Vd.T, Vn.T, Vm.T |
Signed maximum, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
smax v0.4s, v1.4s, v2.4s4ea2642020 64 a2 4e |
|||
| umax | Vd.T, Vn.T, Vm.T |
Unsigned maximum. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
umax v0.4s, v1.4s, v2.4s6ea2642020 64 a2 6e |
|||
| smin | Vd.T, Vn.T, Vm.T |
Signed minimum. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 1 0 1 101 9–5Rn00001 4–0Rd00000 Example
smin v0.4s, v1.4s, v2.4s4ea26c2020 6c a2 4e |
|||
| umin | Vd.T, Vn.T, Vm.T |
Unsigned minimum. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 1 0 1 101 9–5Rn00001 4–0Rd00000 Example
umin v0.4s, v1.4s, v2.4s6ea26c2020 6c a2 6e |
|||
| sabd | Vd.T, Vn.T, Vm.T |
Signed absolute difference. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
sabd v0.4s, v1.4s, v2.4s4ea2742020 74 a2 4e |
|||
| uabd | Vd.T, Vn.T, Vm.T |
Unsigned absolute difference. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
uabd v0.4s, v1.4s, v2.4s6ea2742020 74 a2 6e |
|||
| saba | Vd.T, Vn.T, Vm.T |
Signed absolute difference and accumulate. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
saba v0.4s, v1.4s, v2.4s4ea27c2020 7c a2 4e |
|||
| uaba | Vd.T, Vn.T, Vm.T |
Unsigned absolute difference and accumulate. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–110 1 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
uaba v0.4s, v1.4s, v2.4s6ea27c2020 7c a2 6e |
|||
| add | Vd.T, Vn.T, Vm.T |
Integer add, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
add v0.4s, v1.4s, v2.4s4ea2842020 84 a2 4e |
|||
| sub | Vd.T, Vn.T, Vm.T |
Integer subtract, per lane. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
sub v0.4s, v1.4s, v2.4s6ea2842020 84 a2 6e |
|||
| cmtst | Vd.T, Vn.T, Vm.T |
Test bits: lane != 0 after AND. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–111 0 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
cmtst v0.8b, v1.8b, v2.8b0e228c2020 8c 22 0e |
|||
| cmeq | Vd.T, Vn.T, Vm.T |
Compare equal, per lane. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
cmeq v0.4s, v1.4s, v2.4s6ea28c2020 8c a2 6e |
|||
| mla | Vd.T, Vn.T, Vm.T |
Multiply-accumulate, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
mla v0.4s, v1.4s, v2.4s4ea2942020 94 a2 4e |
|||
| mls | Vd.T, Vn.T, Vm.T |
Multiply-subtract, per lane. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
mls v0.4s, v1.4s, v2.4s6ea2942020 94 a2 6e |
|||
| mul | Vd.T, Vn.T, Vm.T |
Multiply, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
mul v0.4s, v1.4s, v2.4s4ea29c2020 9c a2 4e |
|||
| pmul | Vd.T, Vn.T, Vm.T |
Polynomial multiply (bytes). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–111 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
pmul v0.16b, v1.16b, v2.16b6e229c2020 9c 22 6e |
|||
| smaxp | Vd.T, Vn.T, Vm.T |
Signed pairwise maximum. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
smaxp v0.4s, v1.4s, v2.4s4ea2a42020 a4 a2 4e |
|||
| umaxp | Vd.T, Vn.T, Vm.T |
Unsigned pairwise maximum. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
umaxp v0.4s, v1.4s, v2.4s6ea2a42020 a4 a2 6e |
|||
| sminp | Vd.T, Vn.T, Vm.T |
Signed pairwise minimum. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 1 0 1 101 9–5Rn00001 4–0Rd00000 Example
sminp v0.4s, v1.4s, v2.4s4ea2ac2020 ac a2 4e |
|||
| uminp | Vd.T, Vn.T, Vm.T |
Unsigned pairwise minimum. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 1 0 1 101 9–5Rn00001 4–0Rd00000 Example
uminp v0.4s, v1.4s, v2.4s6ea2ac2020 ac a2 6e |
|||
| sqdmulh | Vd.T, Vn.T, Vm.T |
Signed saturating doubling multiply high. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
sqdmulh v0.4s, v1.4s, v2.4s4ea2b42020 b4 a2 4e |
|||
| sqrdmulh | Vd.T, Vn.T, Vm.T |
Signed saturating rounding doubling multiply high. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
sqrdmulh v0.4s, v1.4s, v2.4s6ea2b42020 b4 a2 6e |
|||
| addp | Vd.T, Vn.T, Vm.T |
Pairwise add. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 211 20–16Rm00010 15–111 0 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
addp v0.4s, v1.4s, v2.4s4ea2bc2020 bc a2 4e |
|||
| and (vec) | Vd.T, Vn.T, Vm.T |
Bitwise AND. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–220 0 211 20–16Rm00010 15–110 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
and v0.16b, v1.16b, v2.16b4e221c2020 1c 22 4e |
|||
| bic (vec) | Vd.T, Vn.T, Vm.T |
Bitwise AND NOT. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–220 1 211 20–16Rm00010 15–110 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
bic v0.16b, v1.16b, v2.16b4e621c2020 1c 62 4e |
|||
| orr (vec) | Vd.T, Vn.T, Vm.T |
Bitwise OR. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–221 0 211 20–16Rm00010 15–110 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
orr v0.16b, v1.16b, v2.16b4ea21c2020 1c a2 4e |
|||
| orn (vec) | Vd.T, Vn.T, Vm.T |
Bitwise OR NOT. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–221 1 211 20–16Rm00010 15–110 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
orn v0.16b, v1.16b, v2.16b4ee21c2020 1c e2 4e |
|||
| eor (vec) | Vd.T, Vn.T, Vm.T |
Bitwise XOR. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–220 0 211 20–16Rm00010 15–110 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
eor v0.16b, v1.16b, v2.16b6e221c2020 1c 22 6e |
|||
| bsl (vec) | Vd.T, Vn.T, Vm.T |
Bitwise select (Vd chooses). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–220 1 211 20–16Rm00010 15–110 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
bsl v0.16b, v1.16b, v2.16b6e621c2020 1c 62 6e |
|||
| bit (vec) | Vd.T, Vn.T, Vm.T |
Bitwise insert if true. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–221 0 211 20–16Rm00010 15–110 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
bit v0.16b, v1.16b, v2.16b6ea21c2020 1c a2 6e |
|||
| bif (vec) | Vd.T, Vn.T, Vm.T |
Bitwise insert if false. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–221 1 211 20–16Rm00010 15–110 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
bif v0.16b, v1.16b, v2.16b6ee21c2020 1c e2 6e |
|||
| sdot | Vd.T, Vn.Tb, Vm.Tb |
Signed dot product of 4-byte groups, accumulated into 32-bit lanes. | DotProd |
|
310 30Q1 290 28–240 1 1 1 0 23–221 0 210 20–16Rm00010 15–111 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
sdot v0.4s, v1.16b, v2.16b4e82942020 94 82 4e |
|||
| udot | Vd.T, Vn.Tb, Vm.Tb |
Unsigned dot product of 4-byte groups. | DotProd |
|
310 30Q1 291 28–240 1 1 1 0 23–221 0 210 20–16Rm00010 15–111 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
udot v0.4s, v1.16b, v2.16b6e82942020 94 82 6e |
|||
| sqrdmlah | Vd.T, Vn.T, Vm.T |
Saturating rounding doubling multiply-accumulate high. | RDM |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 15–111 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
sqrdmlah v0.4s, v1.4s, v2.4s6e82842020 84 82 6e |
|||
| sqrdmlsh | Vd.T, Vn.T, Vm.T |
Saturating rounding doubling multiply-subtract high. | RDM |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 15–111 0 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
sqrdmlsh v0.4s, v1.4s, v2.4s6e828c2020 8c 82 6e |
|||
| SIMD three-same (floating point) | |||
| fmaxnm (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP maximum (IEEE NaN rules). | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
fmaxnm v0.4s, v1.4s, v2.4s4e22c42020 c4 22 4e |
|||
| fminnm (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP minimum (IEEE NaN rules). | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
fminnm v0.4s, v1.4s, v2.4s4ea2c42020 c4 a2 4e |
|||
| fmla (vec) | Vd.T, Vn.T, Vm.T |
Fused multiply-add, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
fmla v0.4s, v1.4s, v2.4s4e22cc2020 cc 22 4e |
|||
| fmls (vec) | Vd.T, Vn.T, Vm.T |
Fused multiply-subtract, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
fmls v0.4s, v1.4s, v2.4s4ea2cc2020 cc a2 4e |
|||
| fadd (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP add. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
fadd v0.4s, v1.4s, v2.4s4e22d42020 d4 22 4e |
|||
| fsub (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP subtract. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
fsub v0.4s, v1.4s, v2.4s4ea2d42020 d4 a2 4e |
|||
| fmulx (vec) | Vd.T, Vn.T, Vm.T |
FP multiply extended (handles 0×inf). | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
fmulx v0.4s, v1.4s, v2.4s4e22dc2020 dc 22 4e |
|||
| fmax (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP maximum. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
fmax v0.4s, v1.4s, v2.4s4e22f42020 f4 22 4e |
|||
| fmin (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP minimum. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
fmin v0.4s, v1.4s, v2.4s4ea2f42020 f4 a2 4e |
|||
| frecps (vec) | Vd.T, Vn.T, Vm.T |
Reciprocal step (Newton-Raphson). | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
frecps v0.4s, v1.4s, v2.4s4e22fc2020 fc 22 4e |
|||
| frsqrts (vec) | Vd.T, Vn.T, Vm.T |
Reciprocal square-root step. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
frsqrts v0.4s, v1.4s, v2.4s4ea2fc2020 fc a2 4e |
|||
| fcmeq (vec) | Vd.T, Vn.T, Vm.T |
FP compare equal, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
fcmeq v0.4s, v1.4s, v2.4s4e22e42020 e4 22 4e |
|||
| fmul (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP multiply. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
fmul v0.4s, v1.4s, v2.4s6e22dc2020 dc 22 6e |
|||
| fcmge (vec) | Vd.T, Vn.T, Vm.T |
FP compare greater or equal. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
fcmge v0.4s, v1.4s, v2.4s6e22e42020 e4 22 6e |
|||
| facge (vec) | Vd.T, Vn.T, Vm.T |
FP absolute compare greater or equal. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 1 0 1 101 9–5Rn00001 4–0Rd00000 Example
facge v0.4s, v1.4s, v2.4s6e22ec2020 ec 22 6e |
|||
| fcmgt (vec) | Vd.T, Vn.T, Vm.T |
FP compare greater than. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
fcmgt v0.4s, v1.4s, v2.4s6ea2e42020 e4 a2 6e |
|||
| facgt (vec) | Vd.T, Vn.T, Vm.T |
FP absolute compare greater than. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 1 0 1 101 9–5Rn00001 4–0Rd00000 Example
facgt v0.4s, v1.4s, v2.4s6ea2ec2020 ec a2 6e |
|||
| fdiv (vec) | Vd.T, Vn.T, Vm.T |
Lane-wise FP divide. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
fdiv v0.4s, v1.4s, v2.4s6e22fc2020 fc 22 6e |
|||
| faddp (vec) | Vd.T, Vn.T, Vm.T |
Pairwise FP add. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
faddp v0.4s, v1.4s, v2.4s6e22d42020 d4 22 6e |
|||
| fmaxp (vec) | Vd.T, Vn.T, Vm.T |
Pairwise FP maximum. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
fmaxp v0.4s, v1.4s, v2.4s6e22f42020 f4 22 6e |
|||
| fminp (vec) | Vd.T, Vn.T, Vm.T |
Pairwise FP minimum. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
fminp v0.4s, v1.4s, v2.4s6ea2f42020 f4 a2 6e |
|||
| fmaxnmp (vec) | Vd.T, Vn.T, Vm.T |
Pairwise FP maximum (NaN rules). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 220 211 20–16Rm00010 15–111 1 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
fmaxnmp v0.4s, v1.4s, v2.4s6e22c42020 c4 22 6e |
|||
| fminnmp (vec) | Vd.T, Vn.T, Vm.T |
Pairwise FP minimum (NaN rules). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
fminnmp v0.4s, v1.4s, v2.4s6ea2c42020 c4 a2 6e |
|||
| fabd (vec) | Vd.T, Vn.T, Vm.T |
FP absolute difference. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 220 211 20–16Rm00010 15–111 1 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
fabd v0.4s, v1.4s, v2.4s6ea2d42020 d4 a2 6e |
|||
| SIMD two-register misc | |||
| rev64 | Vd.T, Vn.T |
Reverse elements in 64-bit groups. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 0 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
rev64 v0.4s, v1.4s4ea0082020 08 a0 4e |
|||
| rev16 (vec) | Vd.T, Vn.T |
Reverse bytes in 16-bit groups. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size00 21–171 0 0 0 0 16–120 0 0 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
rev16 v0.16b, v1.16b4e20182020 18 20 4e |
|||
| rev32 (vec) | Vd.T, Vn.T |
Reverse bytes in 32-bit groups. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size01 21–171 0 0 0 0 16–120 0 0 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
rev32 v0.8h, v1.8h6e60082020 08 60 6e |
|||
| saddlp | Vd.T, Vn.T |
Signed add long pairwise (widen and add pairs). | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
saddlp v0.2d, v1.4s4ea0282020 28 a0 4e |
|||
| uaddlp | Vd.T, Vn.T |
Unsigned add long pairwise. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
uaddlp v0.2d, v1.4s6ea0282020 28 a0 6e |
|||
| sadalp | Vd.T, Vn.T |
Signed add long pairwise and accumulate. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 1 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
sadalp v0.2d, v1.4s4ea0682020 68 a0 4e |
|||
| uadalp | Vd.T, Vn.T |
Unsigned add long pairwise and accumulate. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 1 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
uadalp v0.2d, v1.4s6ea0682020 68 a0 6e |
|||
| suqadd | Vd.T, Vn.T |
Signed saturating accumulate of unsigned value. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
suqadd v0.4s, v1.4s4ea0382020 38 a0 4e |
|||
| usqadd | Vd.T, Vn.T |
Unsigned saturating accumulate of signed value. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
usqadd v0.4s, v1.4s6ea0382020 38 a0 6e |
|||
| cls (vec) | Vd.T, Vn.T |
Count leading sign bits, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
cls v0.4s, v1.4s4ea0482020 48 a0 4e |
|||
| clz (vec) | Vd.T, Vn.T |
Count leading zero bits, per lane. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
clz v0.4s, v1.4s6ea0482020 48 a0 6e |
|||
| cnt (vec) | Vd.T, Vn.T |
Count set bits per byte. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size00 21–171 0 0 0 0 16–120 0 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
cnt v0.16b, v1.16b4e20582020 58 20 4e |
|||
| not | Vd.T, Vn.T |
Bitwise NOT (also written mvn). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–220 0 21–171 0 0 0 0 16–120 0 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
not v0.16b, v1.16b6e20582020 58 20 6e |
|||
| rbit (vec) | Vd.T, Vn.T |
Reverse bit order in each byte. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–220 1 21–171 0 0 0 0 16–120 0 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
rbit v0.16b, v1.16b6e60582020 58 60 6e |
|||
| sqabs | Vd.T, Vn.T |
Signed saturating absolute value. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
sqabs v0.4s, v1.4s4ea0782020 78 a0 4e |
|||
| sqneg | Vd.T, Vn.T |
Signed saturating negate. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 0 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
sqneg v0.4s, v1.4s6ea0782020 78 a0 6e |
|||
| cmgt (zero) | Vd.T, Vn.T |
Compare greater than zero, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 1 0 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
cmgt v0.4s, v1.4s, #04ea0882020 88 a0 4e |
|||
| cmge (zero) | Vd.T, Vn.T |
Compare greater than or equal zero. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 1 0 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
cmge v0.4s, v1.4s, #06ea0882020 88 a0 6e |
|||
| cmeq (zero) | Vd.T, Vn.T |
Compare equal to zero. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 1 0 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
cmeq v0.4s, v1.4s, #04ea0982020 98 a0 4e |
|||
| cmle (zero) | Vd.T, Vn.T |
Compare less than or equal zero. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 1 0 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
cmle v0.4s, v1.4s, #06ea0982020 98 a0 6e |
|||
| cmlt (zero) | Vd.T, Vn.T |
Compare less than zero. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 1 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
cmlt v0.4s, v1.4s, #04ea0a82020 a8 a0 4e |
|||
| abs (vec) | Vd.T, Vn.T |
Absolute value, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
abs v0.4s, v1.4s4ea0b82020 b8 a0 4e |
|||
| neg (vec) | Vd.T, Vn.T |
Negate, per lane. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 0 0 0 0 16–120 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
neg v0.4s, v1.4s6ea0b82020 b8 a0 6e |
|||
| xtn | Vd.T, Vn.T |
Extract narrow: take the low half of each lane. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size01 21–171 0 0 0 0 16–121 0 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
xtn v0.4h, v1.4s0e61282020 28 61 0e |
|||
| sqxtn | Vd.T, Vn.T |
Signed saturating extract narrow. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size01 21–171 0 0 0 0 16–121 0 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
sqxtn v0.4h, v1.4s0e61482020 48 61 0e |
|||
| uqxtn | Vd.T, Vn.T |
Unsigned saturating extract narrow. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size01 21–171 0 0 0 0 16–121 0 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
uqxtn v0.4h, v1.4s2e61482020 48 61 2e |
|||
| sqxtun | Vd.T, Vn.T |
Signed saturating extract unsigned narrow. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size01 21–171 0 0 0 0 16–121 0 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
sqxtun v0.4h, v1.4s2e61282020 28 61 2e |
|||
| shll | Vd.T, Vn.T |
Shift left long by the element size. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size01 21–171 0 0 0 0 16–121 0 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
shll v0.4s, v1.4h, #162e61382020 38 61 2e |
|||
| frintn (vec) | Vd.T, Vn.T |
Round to integral, nearest ties even. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 0 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
frintn v0.4s, v1.4s4e21882020 88 21 4e |
|||
| frintm (vec) | Vd.T, Vn.T |
Round to integral, toward -inf. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 0 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
frintm v0.4s, v1.4s4e21982020 98 21 4e |
|||
| frintp (vec) | Vd.T, Vn.T |
Round to integral, toward +inf. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 0 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
frintp v0.4s, v1.4s4ea1882020 88 a1 4e |
|||
| frintz (vec) | Vd.T, Vn.T |
Round to integral, toward zero. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 0 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
frintz v0.4s, v1.4s4ea1982020 98 a1 4e |
|||
| frinta (vec) | Vd.T, Vn.T |
Round to integral, nearest ties away. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 0 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
frinta v0.4s, v1.4s6e21882020 88 21 6e |
|||
| frintx (vec) | Vd.T, Vn.T |
Round to integral using current mode (raise Inexact). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 0 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
frintx v0.4s, v1.4s6e21982020 98 21 6e |
|||
| frinti (vec) | Vd.T, Vn.T |
Round to integral using current mode. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 0 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
frinti v0.4s, v1.4s6ea1982020 98 a1 6e |
|||
| fcvtns (vec) | Vd.T, Vn.T |
FP convert to signed int, nearest ties even. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtns v0.4s, v1.4s4e21a82020 a8 21 4e |
|||
| fcvtms (vec) | Vd.T, Vn.T |
FP convert to signed int, toward -inf. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtms v0.4s, v1.4s4e21b82020 b8 21 4e |
|||
| fcvtps (vec) | Vd.T, Vn.T |
FP convert to signed int, toward +inf. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtps v0.4s, v1.4s4ea1a82020 a8 a1 4e |
|||
| fcvtzs (vec) | Vd.T, Vn.T |
FP convert to signed int, toward zero. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtzs v0.4s, v1.4s4ea1b82020 b8 a1 4e |
|||
| fcvtas (vec) | Vd.T, Vn.T |
FP convert to signed int, nearest ties away. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtas v0.4s, v1.4s4e21c82020 c8 21 4e |
|||
| fcvtnu (vec) | Vd.T, Vn.T |
FP convert to unsigned int, nearest ties even. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtnu v0.4s, v1.4s6e21a82020 a8 21 6e |
|||
| fcvtmu (vec) | Vd.T, Vn.T |
FP convert to unsigned int, toward -inf. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtmu v0.4s, v1.4s6e21b82020 b8 21 6e |
|||
| fcvtpu (vec) | Vd.T, Vn.T |
FP convert to unsigned int, toward +inf. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtpu v0.4s, v1.4s6ea1a82020 a8 a1 6e |
|||
| fcvtzu (vec) | Vd.T, Vn.T |
FP convert to unsigned int, toward zero. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtzu v0.4s, v1.4s6ea1b82020 b8 a1 6e |
|||
| fcvtau (vec) | Vd.T, Vn.T |
FP convert to unsigned int, nearest ties away. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtau v0.4s, v1.4s6e21c82020 c8 21 6e |
|||
| scvtf (vec) | Vd.T, Vn.T |
Convert signed integer lanes to FP. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
scvtf v0.4s, v1.4s4e21d82020 d8 21 4e |
|||
| ucvtf (vec) | Vd.T, Vn.T |
Convert unsigned integer lanes to FP. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 1 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
ucvtf v0.4s, v1.4s6e21d82020 d8 21 6e |
|||
| fabs (vec) | Vd.T, Vn.T |
FP absolute value, per lane. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–120 1 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fabs v0.4s, v1.4s4ea0f82020 f8 a0 4e |
|||
| fneg (vec) | Vd.T, Vn.T |
FP negate, per lane. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–120 1 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fneg v0.4s, v1.4s6ea0f82020 f8 a0 6e |
|||
| fsqrt (vec) | Vd.T, Vn.T |
FP square root, per lane. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fsqrt v0.4s, v1.4s6ea1f82020 f8 a1 6e |
|||
| frecpe | Vd.T, Vn.T |
FP reciprocal estimate. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
frecpe v0.4s, v1.4s4ea1d82020 d8 a1 4e |
|||
| frsqrte | Vd.T, Vn.T |
FP reciprocal square-root estimate. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
frsqrte v0.4s, v1.4s6ea1d82020 d8 a1 6e |
|||
| fcmgt (zero) | Vd.T, Vn.T |
FP compare greater than zero. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–120 1 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcmgt v0.4s, v1.4s, #0.04ea0c82020 c8 a0 4e |
|||
| fcmeq (zero) | Vd.T, Vn.T |
FP compare equal to zero. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–120 1 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcmeq v0.4s, v1.4s, #0.04ea0d82020 d8 a0 4e |
|||
| fcmlt (zero) | Vd.T, Vn.T |
FP compare less than zero. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–120 1 1 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcmlt v0.4s, v1.4s, #0.04ea0e82020 e8 a0 4e |
|||
| fcmge (zero) | Vd.T, Vn.T |
FP compare greater or equal zero. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–120 1 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcmge v0.4s, v1.4s, #0.06ea0c82020 c8 a0 6e |
|||
| fcmle (zero) | Vd.T, Vn.T |
FP compare less or equal zero. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–120 1 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcmle v0.4s, v1.4s, #0.06ea0d82020 d8 a0 6e |
|||
| fcvtn | Vd.Tb, Vn.Ta |
FP convert to narrower precision (e.g. 2D to 2S). | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 0 1 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtn v0.4h, v1.4s0e21682020 68 21 0e |
|||
| fcvtl | Vd.Ta, Vn.Tb |
FP convert to wider precision. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 230 22sz0 21–171 0 0 0 0 16–121 0 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtl v0.4s, v1.4h0e21782020 78 21 0e |
|||
| fcvtxn | Vd.Tb, Vn.Ta |
FP convert narrow, round to odd. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 230 22sz1 21–171 0 0 0 0 16–121 0 1 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtxn v0.2s, v1.2d2e61682020 68 61 2e |
|||
| frecpx (scalar) | Sd, Sn |
Scalar FP reciprocal exponent. | SIMD |
|
310 301 290 28–241 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
frecpx s0, s15ea1f82020 f8 a1 5e |
|||
| urecpe | Vd.T, Vn.T |
Unsigned integer reciprocal estimate. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
urecpe v0.4s, v1.4s4ea1c82020 c8 a1 4e |
|||
| ursqrte | Vd.T, Vn.T |
Unsigned integer reciprocal square-root estimate. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
ursqrte v0.4s, v1.4s6ea1c82020 c8 a1 6e |
|||
| SIMD across lanes | |||
| saddlv | Rd, Vn.T |
Signed sum of all lanes, into a wider scalar. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size01 21–171 1 0 0 0 16–120 0 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
saddlv s0, v1.8h4e70382020 38 70 4e |
|||
| uaddlv | Rd, Vn.T |
Unsigned sum of all lanes, widened. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size01 21–171 1 0 0 0 16–120 0 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
uaddlv s0, v1.8h6e70382020 38 70 6e |
|||
| smaxv | Rd, Vn.T |
Signed maximum across all lanes. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 1 0 0 0 16–120 1 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
smaxv s0, v1.4s4eb0a82020 a8 b0 4e |
|||
| sminv | Rd, Vn.T |
Signed minimum across all lanes. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 1 0 0 0 16–121 1 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
sminv s0, v1.4s4eb1a82020 a8 b1 4e |
|||
| umaxv | Rd, Vn.T |
Unsigned maximum across all lanes. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 1 0 0 0 16–120 1 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
umaxv s0, v1.4s6eb0a82020 a8 b0 6e |
|||
| uminv | Rd, Vn.T |
Unsigned minimum across all lanes. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 23–22size10 21–171 1 0 0 0 16–121 1 0 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
uminv s0, v1.4s6eb1a82020 a8 b1 6e |
|||
| addv | Rd, Vn.T |
Add all lanes into one scalar. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 21–171 1 0 0 0 16–121 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
addv s0, v1.4s4eb1b82020 b8 b1 4e |
|||
| fmaxv | Sd, Vn.4S |
FP maximum across all lanes. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 22sz0 21–171 1 0 0 0 16–120 1 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fmaxv s0, v1.4s6e30f82020 f8 30 6e |
|||
| fminv | Sd, Vn.4S |
FP minimum across all lanes. | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 1 0 0 0 16–120 1 1 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fminv s0, v1.4s6eb0f82020 f8 b0 6e |
|||
| fmaxnmv | Sd, Vn.4S |
FP maximum across lanes (NaN rules). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 230 22sz0 21–171 1 0 0 0 16–120 1 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fmaxnmv s0, v1.4s6e30c82020 c8 30 6e |
|||
| fminnmv | Sd, Vn.4S |
FP minimum across lanes (NaN rules). | SIMD |
|
310 30Q1 291 28–240 1 1 1 0 231 22sz0 21–171 1 0 0 0 16–120 1 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
fminnmv s0, v1.4s6eb0c82020 c8 b0 6e |
|||
| SIMD three-different | |||
| saddl | Vd.8h, Vn.8b, Vm.8b |
Signed add long (widen operands then add). | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 0 0 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
saddl v0.8h, v1.8b, v2.8b0e22002020 00 22 0e |
|||
| uaddl | Vd.8h, Vn.8b, Vm.8b |
Unsigned add long. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 0 0 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
uaddl v0.8h, v1.8b, v2.8b2e22002020 00 22 2e |
|||
| saddw | Vd.8h, Vn.8h, Vm.8b |
Signed add wide (one wide, one narrow operand). | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 0 0 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
saddw v0.8h, v1.8h, v2.8b0e22102020 10 22 0e |
|||
| uaddw | Vd.8h, Vn.8h, Vm.8b |
Unsigned add wide. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 0 0 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
uaddw v0.8h, v1.8h, v2.8b2e22102020 10 22 2e |
|||
| ssubl | Vd.8h, Vn.8b, Vm.8b |
Signed subtract long. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 0 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
ssubl v0.8h, v1.8b, v2.8b0e22202020 20 22 0e |
|||
| usubl | Vd.8h, Vn.8b, Vm.8b |
Unsigned subtract long. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 0 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
usubl v0.8h, v1.8b, v2.8b2e22202020 20 22 2e |
|||
| ssubw | Vd.8h, Vn.8h, Vm.8b |
Signed subtract wide. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 0 1 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
ssubw v0.8h, v1.8h, v2.8b0e22302020 30 22 0e |
|||
| usubw | Vd.8h, Vn.8h, Vm.8b |
Unsigned subtract wide. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 0 1 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
usubw v0.8h, v1.8h, v2.8b2e22302020 30 22 2e |
|||
| addhn | Vd.8b, Vn.8h, Vm.8h |
Add and narrow, taking the high half. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 1 0 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
addhn v0.8b, v1.8h, v2.8h0e22402020 40 22 0e |
|||
| raddhn | Vd.8b, Vn.8h, Vm.8h |
Rounding add high narrow. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 1 0 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
raddhn v0.8b, v1.8h, v2.8h2e22402020 40 22 2e |
|||
| subhn | Vd.8b, Vn.8h, Vm.8h |
Subtract and narrow, high half. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 1 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
subhn v0.8b, v1.8h, v2.8h0e22602020 60 22 0e |
|||
| rsubhn | Vd.8b, Vn.8h, Vm.8h |
Rounding subtract high narrow. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 1 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
rsubhn v0.8b, v1.8h, v2.8h2e22602020 60 22 2e |
|||
| sabal | Vd.8h, Vn.8b, Vm.8b |
Signed absolute difference and accumulate long. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 1 0 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
sabal v0.8h, v1.8b, v2.8b0e22502020 50 22 0e |
|||
| uabal | Vd.8h, Vn.8b, Vm.8b |
Unsigned absolute difference and accumulate long. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 1 0 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
uabal v0.8h, v1.8b, v2.8b2e22502020 50 22 2e |
|||
| sabdl | Vd.8h, Vn.8b, Vm.8b |
Signed absolute difference long. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 1 1 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
sabdl v0.8h, v1.8b, v2.8b0e22702020 70 22 0e |
|||
| uabdl | Vd.8h, Vn.8b, Vm.8b |
Unsigned absolute difference long. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–120 1 1 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
uabdl v0.8h, v1.8b, v2.8b2e22702020 70 22 2e |
|||
| smlal | Vd.8h, Vn.8b, Vm.8b |
Signed multiply-accumulate long. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–121 0 0 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
smlal v0.8h, v1.8b, v2.8b0e22802020 80 22 0e |
|||
| umlal | Vd.8h, Vn.8b, Vm.8b |
Unsigned multiply-accumulate long. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–121 0 0 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
umlal v0.8h, v1.8b, v2.8b2e22802020 80 22 2e |
|||
| smlsl | Vd.8h, Vn.8b, Vm.8b |
Signed multiply-subtract long. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–121 0 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
smlsl v0.8h, v1.8b, v2.8b0e22a02020 a0 22 0e |
|||
| umlsl | Vd.8h, Vn.8b, Vm.8b |
Unsigned multiply-subtract long. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–121 0 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
umlsl v0.8h, v1.8b, v2.8b2e22a02020 a0 22 2e |
|||
| smull (vec) | Vd.8h, Vn.8b, Vm.8b |
Signed multiply long. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–121 1 0 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
smull v0.8h, v1.8b, v2.8b0e22c02020 c0 22 0e |
|||
| umull (vec) | Vd.8h, Vn.8b, Vm.8b |
Unsigned multiply long. | SIMD |
|
310 30Q0 291 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–121 1 0 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
umull v0.8h, v1.8b, v2.8b2e22c02020 c0 22 2e |
|||
| sqdmlal | Vd.4s, Vn.4h, Vm.4h |
Signed saturating doubling multiply-accumulate long. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size01 211 20–16Rm00010 15–121 0 0 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
sqdmlal v0.4s, v1.4h, v2.4h0e62902020 90 62 0e |
|||
| sqdmlsl | Vd.4s, Vn.4h, Vm.4h |
Signed saturating doubling multiply-subtract long. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size01 211 20–16Rm00010 15–121 0 1 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
sqdmlsl v0.4s, v1.4h, v2.4h0e62b02020 b0 62 0e |
|||
| sqdmull | Vd.4s, Vn.4h, Vm.4h |
Signed saturating doubling multiply long. | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size01 211 20–16Rm00010 15–121 1 0 1 11–100 0 9–5Rn00001 4–0Rd00000 Example
sqdmull v0.4s, v1.4h, v2.4h0e62d02020 d0 62 0e |
|||
| pmull | Vd.8h, Vn.8b, Vm.8b |
Polynomial multiply long (also .1q from .1d for GHASH). | SIMD |
|
310 30Q0 290 28–240 1 1 1 0 23–22size00 211 20–16Rm00010 15–121 1 1 0 11–100 0 9–5Rn00001 4–0Rd00000 Example
pmull v0.8h, v1.8b, v2.8b0e22e02020 e0 22 0e |
|||
| SIMD modified immediate | |||
| movi | Vd.T, #imm{, lsl #s} |
Set each lane to an 8-bit immediate, optionally shifted or expanded. | SIMD |
|
310 30Q1 290 28–190 1 1 1 1 0 0 0 0 0 18a0 17b0 16c0 15–12cmode0010 11–100 1 9d0 8e0 7f0 6g0 5h1 4–0Rd00000 Example
movi v0.4s, #1, lsl #84f00242020 24 00 4f |
|||
| mvni | Vd.T, #imm{, lsl #s} |
Set each lane to the bitwise NOT of the immediate pattern. | SIMD |
|
310 30Q1 291 28–190 1 1 1 1 0 0 0 0 0 18a0 17b0 16c0 15–12cmode0010 11–100 1 9d0 8e0 7f0 6g0 5h1 4–0Rd00000 Example
mvni v0.4s, #1, lsl #86f00242020 24 00 6f |
|||
| orr (imm) | Vd.T, #imm{, lsl #s} |
OR an immediate into each lane. | SIMD |
|
310 30Q1 290 28–190 1 1 1 1 0 0 0 0 0 18a0 17b0 16c0 15cmode00 14–13cmode101 121 11–100 1 9d0 8e0 7f0 6g0 5h1 4–0Rd00000 Example
orr v0.4s, #1, lsl #84f00342020 34 00 4f |
|||
| bic (imm) | Vd.T, #imm{, lsl #s} |
Clear bits selected by the immediate in each lane. | SIMD |
|
310 30Q1 291 28–190 1 1 1 1 0 0 0 0 0 18a0 17b0 16c0 15cmode00 14–13cmode101 121 11–100 1 9d0 8e0 7f0 6g0 5h1 4–0Rd00000 Example
bic v0.4s, #1, lsl #86f00342020 34 00 6f |
|||
| fmov (vec imm) | Vd.T, #fimm |
Broadcast an 8-bit-encoded FP constant to every lane. | SIMD |
|
310 30Q1 29op0 28–190 1 1 1 1 0 0 0 0 0 18a0 17b1 16c1 15–121 1 1 1 11–100 1 9d1 8e0 7f0 6g0 5h0 4–0Rd00000 Example
fmov v0.4s, #1.04f03f60000 f6 03 4f |
|||
| SIMD shift by immediate | |||
| sshr | Vd.T, Vn.T, #sh |
Signed shift right by immediate. | SIMD |
|
310 30Q1 290 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–110 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
sshr v0.4s, v1.4s, #34f3d042020 04 3d 4f |
|||
| ushr | Vd.T, Vn.T, #sh |
Unsigned shift right by immediate. | SIMD |
|
310 30Q1 291 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–110 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
ushr v0.4s, v1.4s, #36f3d042020 04 3d 6f |
|||
| ssra | Vd.T, Vn.T, #sh |
Signed shift right and accumulate. | SIMD |
|
310 30Q1 290 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–110 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
ssra v0.4s, v1.4s, #34f3d142020 14 3d 4f |
|||
| usra | Vd.T, Vn.T, #sh |
Unsigned shift right and accumulate. | SIMD |
|
310 30Q1 291 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–110 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
usra v0.4s, v1.4s, #36f3d142020 14 3d 6f |
|||
| srshr | Vd.T, Vn.T, #sh |
Signed rounding shift right. | SIMD |
|
310 30Q1 290 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–110 0 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
srshr v0.4s, v1.4s, #34f3d242020 24 3d 4f |
|||
| urshr | Vd.T, Vn.T, #sh |
Unsigned rounding shift right. | SIMD |
|
310 30Q1 291 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–110 0 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
urshr v0.4s, v1.4s, #36f3d242020 24 3d 6f |
|||
| srsra | Vd.T, Vn.T, #sh |
Signed rounding shift right and accumulate. | SIMD |
|
310 30Q1 290 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–110 0 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
srsra v0.4s, v1.4s, #34f3d342020 34 3d 4f |
|||
| ursra | Vd.T, Vn.T, #sh |
Unsigned rounding shift right and accumulate. | SIMD |
|
310 30Q1 291 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–110 0 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
ursra v0.4s, v1.4s, #36f3d342020 34 3d 6f |
|||
| shl (vec) | Vd.T, Vn.T, #sh |
Shift left by immediate. | SIMD |
|
310 30Q1 290 28–230 1 1 1 1 0 22–19immh0100 18–16immb011 15–110 1 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
shl v0.4s, v1.4s, #34f23542020 54 23 4f |
|||
| sli | Vd.T, Vn.T, #sh |
Shift left and insert (keep unshifted bits). | SIMD |
|
310 30Q1 291 28–230 1 1 1 1 0 22–19immh0100 18–16immb011 15–110 1 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
sli v0.4s, v1.4s, #36f23542020 54 23 6f |
|||
| sri | Vd.T, Vn.T, #sh |
Shift right and insert. | SIMD |
|
310 30Q1 291 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–110 1 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
sri v0.4s, v1.4s, #36f3d442020 44 3d 6f |
|||
| sqshl (imm) | Vd.T, Vn.T, #sh |
Signed saturating shift left by immediate. | SIMD |
|
310 30Q1 290 28–230 1 1 1 1 0 22–19immh0100 18–16immb011 15–110 1 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
sqshl v0.4s, v1.4s, #34f23742020 74 23 4f |
|||
| uqshl (imm) | Vd.T, Vn.T, #sh |
Unsigned saturating shift left by immediate. | SIMD |
|
310 30Q1 291 28–230 1 1 1 1 0 22–19immh0100 18–16immb011 15–110 1 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
uqshl v0.4s, v1.4s, #36f23742020 74 23 6f |
|||
| sqshlu | Vd.T, Vn.T, #sh |
Signed saturating shift left unsigned. | SIMD |
|
310 30Q1 291 28–230 1 1 1 1 0 22–19immh0100 18–16immb011 15–110 1 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
sqshlu v0.4s, v1.4s, #36f23642020 64 23 6f |
|||
| shrn | Vd.Tb, Vn.Ta, #sh |
Shift right and narrow. | SIMD |
|
310 30Q0 290 28–230 1 1 1 1 0 22–19immh0011 18–16immb101 15–111 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
shrn v0.4h, v1.4s, #30f1d842020 84 1d 0f |
|||
| rshrn | Vd.Tb, Vn.Ta, #sh |
Rounding shift right and narrow. | SIMD |
|
310 30Q0 290 28–230 1 1 1 1 0 22–19immh0011 18–16immb101 15–111 0 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
rshrn v0.4h, v1.4s, #30f1d8c2020 8c 1d 0f |
|||
| sqshrn | Vd.Tb, Vn.Ta, #sh |
Signed saturating shift right and narrow. | SIMD |
|
310 30Q0 290 28–230 1 1 1 1 0 22–19immh0011 18–16immb101 15–111 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
sqshrn v0.4h, v1.4s, #30f1d942020 94 1d 0f |
|||
| sqrshrn | Vd.Tb, Vn.Ta, #sh |
Signed saturating rounding shift right narrow. | SIMD |
|
310 30Q0 290 28–230 1 1 1 1 0 22–19immh0011 18–16immb101 15–111 0 0 1 1 101 9–5Rn00001 4–0Rd00000 Example
sqrshrn v0.4h, v1.4s, #30f1d9c2020 9c 1d 0f |
|||
| sqshrun | Vd.Tb, Vn.Ta, #sh |
Signed saturating shift right unsigned narrow. | SIMD |
|
310 30Q0 291 28–230 1 1 1 1 0 22–19immh0011 18–16immb101 15–111 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
sqshrun v0.4h, v1.4s, #32f1d842020 84 1d 2f |
|||
| uqshrn | Vd.Tb, Vn.Ta, #sh |
Unsigned saturating shift right and narrow. | SIMD |
|
310 30Q0 291 28–230 1 1 1 1 0 22–19immh0011 18–16immb101 15–111 0 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
uqshrn v0.4h, v1.4s, #32f1d942020 94 1d 2f |
|||
| sshll | Vd.Ta, Vn.Tb, #sh |
Signed shift left long. | SIMD |
|
310 30Q0 290 28–230 1 1 1 1 0 22–19immh0010 18–16immb011 15–111 0 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
sshll v0.4s, v1.4h, #30f13a42020 a4 13 0f |
|||
| ushll | Vd.Ta, Vn.Tb, #sh |
Unsigned shift left long. | SIMD |
|
310 30Q0 291 28–230 1 1 1 1 0 22–19immh0010 18–16immb011 15–111 0 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
ushll v0.4s, v1.4h, #32f13a42020 a4 13 2f |
|||
| scvtf (vec,fixed) | Vd.T, Vn.T, #fbits |
Convert fixed-point lanes to FP. | SIMD |
|
310 30Q1 290 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–111 1 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
scvtf v0.4s, v1.4s, #34f3de42020 e4 3d 4f |
|||
| fcvtzs (vec,fixed) | Vd.T, Vn.T, #fbits |
Convert FP lanes to signed fixed-point. | SIMD |
|
310 30Q1 290 28–230 1 1 1 1 0 22–19immh0111 18–16immb101 15–111 1 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
fcvtzs v0.4s, v1.4s, #34f3dfc2020 fc 3d 4f |
|||
| SIMD by element | |||
| mul (elem) | Vd.T, Vn.T, Vm.Ts[i] |
Multiply by a single element. | SIMD |
|
310 30Q1 290 28–240 1 1 1 1 23–22size10 21L1 20M0 19–16Rm0010 15–121 0 0 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
mul v0.4s, v1.4s, v2.s[1]4fa2802020 80 a2 4f |
|||
| mla (elem) | Vd.T, Vn.T, Vm.Ts[i] |
Multiply-accumulate by element. | SIMD |
|
310 30Q1 291 28–240 1 1 1 1 23–22size10 21L1 20M0 19–16Rm0010 15–120 0 0 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
mla v0.4s, v1.4s, v2.s[1]6fa2002020 00 a2 6f |
|||
| mls (elem) | Vd.T, Vn.T, Vm.Ts[i] |
Multiply-subtract by element. | SIMD |
|
310 30Q1 291 28–240 1 1 1 1 23–22size10 21L1 20M0 19–16Rm0010 15–120 1 0 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
mls v0.4s, v1.4s, v2.s[1]6fa2402020 40 a2 6f |
|||
| smlal (elem) | Vd.4s, Vn.4h, Vm.h[i] |
Signed multiply-accumulate long by element. | SIMD |
|
310 30Q0 290 28–240 1 1 1 1 23–22size01 21L0 20M1 19–16Rm0010 15–120 0 1 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
smlal v0.4s, v1.4h, v2.h[1]0f52202020 20 52 0f |
|||
| umlal (elem) | Vd.4s, Vn.4h, Vm.h[i] |
Unsigned multiply-accumulate long by element. | SIMD |
|
310 30Q0 291 28–240 1 1 1 1 23–22size01 21L0 20M1 19–16Rm0010 15–120 0 1 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
umlal v0.4s, v1.4h, v2.h[1]2f52202020 20 52 2f |
|||
| smlsl (elem) | Vd.4s, Vn.4h, Vm.h[i] |
Signed multiply-subtract long by element. | SIMD |
|
310 30Q0 290 28–240 1 1 1 1 23–22size01 21L0 20M1 19–16Rm0010 15–120 1 1 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
smlsl v0.4s, v1.4h, v2.h[1]0f52602020 60 52 0f |
|||
| umlsl (elem) | Vd.4s, Vn.4h, Vm.h[i] |
Unsigned multiply-subtract long by element. | SIMD |
|
310 30Q0 291 28–240 1 1 1 1 23–22size01 21L0 20M1 19–16Rm0010 15–120 1 1 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
umlsl v0.4s, v1.4h, v2.h[1]2f52602020 60 52 2f |
|||
| smull (elem) | Vd.4s, Vn.4h, Vm.h[i] |
Signed multiply long by element. | SIMD |
|
310 30Q0 290 28–240 1 1 1 1 23–22size01 21L0 20M1 19–16Rm0010 15–121 0 1 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
smull v0.4s, v1.4h, v2.h[1]0f52a02020 a0 52 0f |
|||
| umull (elem) | Vd.4s, Vn.4h, Vm.h[i] |
Unsigned multiply long by element. | SIMD |
|
310 30Q0 291 28–240 1 1 1 1 23–22size01 21L0 20M1 19–16Rm0010 15–121 0 1 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
umull v0.4s, v1.4h, v2.h[1]2f52a02020 a0 52 2f |
|||
| sqdmlal (elem) | Vd.4s, Vn.4h, Vm.h[i] |
Saturating doubling multiply-accumulate long by element. | SIMD |
|
310 30Q0 290 28–240 1 1 1 1 23–22size01 21L0 20M1 19–16Rm0010 15–120 0 1 1 11H0 100 9–5Rn00001 4–0Rd00000 Example
sqdmlal v0.4s, v1.4h, v2.h[1]0f52302020 30 52 0f |
|||
| sqdmlsl (elem) | Vd.4s, Vn.4h, Vm.h[i] |
Saturating doubling multiply-subtract long by element. | SIMD |
|
310 30Q0 290 28–240 1 1 1 1 23–22size01 21L0 20M1 19–16Rm0010 15–120 1 1 1 11H0 100 9–5Rn00001 4–0Rd00000 Example
sqdmlsl v0.4s, v1.4h, v2.h[1]0f52702020 70 52 0f |
|||
| sqdmull (elem) | Vd.4s, Vn.4h, Vm.h[i] |
Saturating doubling multiply long by element. | SIMD |
|
310 30Q0 290 28–240 1 1 1 1 23–22size01 21L0 20M1 19–16Rm0010 15–121 0 1 1 11H0 100 9–5Rn00001 4–0Rd00000 Example
sqdmull v0.4s, v1.4h, v2.h[1]0f52b02020 b0 52 0f |
|||
| sqdmulh (elem) | Vd.T, Vn.T, Vm.Ts[i] |
Saturating doubling multiply high by element. | SIMD |
|
310 30Q1 290 28–240 1 1 1 1 23–22size10 21L1 20M0 19–16Rm0010 15–121 1 0 0 11H0 100 9–5Rn00001 4–0Rd00000 Example
sqdmulh v0.4s, v1.4s, v2.s[1]4fa2c02020 c0 a2 4f |
|||
| sqrdmulh (elem) | Vd.T, Vn.T, Vm.Ts[i] |
Saturating rounding doubling multiply high by element. | SIMD |
|
310 30Q1 290 28–240 1 1 1 1 23–22size10 21L1 20M0 19–16Rm0010 15–121 1 0 1 11H0 100 9–5Rn00001 4–0Rd00000 Example
sqrdmulh v0.4s, v1.4s, v2.s[1]4fa2d02020 d0 a2 4f |
|||
| fmla (elem) | Vd.T, Vn.T, Vm.Ts[i] |
FP fused multiply-add by element. | SIMD |
|
310 30Q1 290 28–240 1 1 1 1 231 22sz0 21L1 20M0 19–16Rm0010 15–120 0 0 1 11H0 100 9–5Rn00001 4–0Rd00000 Example
fmla v0.4s, v1.4s, v2.s[1]4fa2102020 10 a2 4f |
|||
| fmls (elem) | Vd.T, Vn.T, Vm.Ts[i] |
FP fused multiply-subtract by element. | SIMD |
|
310 30Q1 290 28–240 1 1 1 1 231 22sz0 21L1 20M0 19–16Rm0010 15–120 1 0 1 11H0 100 9–5Rn00001 4–0Rd00000 Example
fmls v0.4s, v1.4s, v2.s[1]4fa2502020 50 a2 4f |
|||
| fmul (elem) | Vd.T, Vn.T, Vm.Ts[i] |
FP multiply by element. | SIMD |
|
310 30Q1 290 28–240 1 1 1 1 231 22sz0 21L1 20M0 19–16Rm0010 15–121 0 0 1 11H0 100 9–5Rn00001 4–0Rd00000 Example
fmul v0.4s, v1.4s, v2.s[1]4fa2902020 90 a2 4f |
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| fmulx (elem) | Vd.T, Vn.T, Vm.Ts[i] |
FP multiply extended by element. | SIMD |
|
310 30Q1 291 28–240 1 1 1 1 231 22sz0 21L1 20M0 19–16Rm0010 15–121 0 0 1 11H0 100 9–5Rn00001 4–0Rd00000 Example
fmulx v0.4s, v1.4s, v2.s[1]6fa2902020 90 a2 6f |
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| SIMD permute | |||
| uzp1 | Vd.T, Vn.T, Vm.T |
Deinterleave, even-indexed elements. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 150 14–120 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
uzp1 v0.4s, v1.4s, v2.4s4e82182020 18 82 4e |
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| uzp2 | Vd.T, Vn.T, Vm.T |
Deinterleave, odd-indexed elements. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 150 14–121 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
uzp2 v0.4s, v1.4s, v2.4s4e82582020 58 82 4e |
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| trn1 | Vd.T, Vn.T, Vm.T |
Transpose, even-indexed elements. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 150 14–120 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
trn1 v0.4s, v1.4s, v2.4s4e82282020 28 82 4e |
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| trn2 | Vd.T, Vn.T, Vm.T |
Transpose, odd-indexed elements. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 150 14–121 1 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
trn2 v0.4s, v1.4s, v2.4s4e82682020 68 82 4e |
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| zip1 (vec) | Vd.T, Vn.T, Vm.T |
Interleave low halves. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 150 14–120 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
zip1 v0.4s, v1.4s, v2.4s4e82382020 38 82 4e |
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| zip2 | Vd.T, Vn.T, Vm.T |
Interleave high halves. | SIMD |
|
310 30Q1 290 28–240 1 1 1 0 23–22size10 210 20–16Rm00010 150 14–121 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
zip2 v0.4s, v1.4s, v2.4s4e82782020 78 82 4e |
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| SIMD table lookup | |||
| tbl (1 reg) | Vd.T, {Vn.16B}, Vm.T |
Byte table lookup, one table register. | SIMD |
|
310 30Q1 29–240 0 1 1 1 0 23–220 0 210 20–16Rm00010 150 14–130 0 120 11–100 0 9–5Rn00001 4–0Rd00000 Example
tbl v0.16b, {v1.16b}, v2.16b4e02002020 00 02 4e |
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| tbl (2 reg) | Vd.T, {Vn.16B, Vn+1.16B}, Vm.T |
Byte table lookup across two consecutive registers. | SIMD |
|
310 30Q1 29–240 0 1 1 1 0 23–220 0 210 20–16Rm00011 150 14–130 1 120 11–100 0 9–5Rn00001 4–0Rd00000 Example
tbl v0.16b, {v1.16b, v2.16b}, v3.16b4e03202020 20 03 4e |
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| tbl (3 reg) | Vd.T, {Vn..Vn+2.16B}, Vm.T |
Byte table lookup across three registers. | SIMD |
|
310 30Q1 29–240 0 1 1 1 0 23–220 0 210 20–16Rm00100 150 14–131 0 120 11–100 0 9–5Rn00001 4–0Rd00000 Example
tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v4.16b4e04402020 40 04 4e |
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| tbl (4 reg) | Vd.T, {Vn..Vn+3.16B}, Vm.T |
Byte table lookup across four registers. | SIMD |
|
310 30Q1 29–240 0 1 1 1 0 23–220 0 210 20–16Rm00101 150 14–131 1 120 11–100 0 9–5Rn00001 4–0Rd00000 Example
tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v5.16b4e05602020 60 05 4e |
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| tbx (1 reg) | Vd.T, {Vn.16B}, Vm.T |
Table lookup, keeping Vd for out-of-range indices. | SIMD |
|
310 30Q1 29–240 0 1 1 1 0 23–220 0 210 20–16Rm00010 150 14–130 0 121 11–100 0 9–5Rn00001 4–0Rd00000 Example
tbx v0.16b, {v1.16b}, v2.16b4e02102020 10 02 4e |
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| SIMD load/store structures | |||
| ld1 (1 reg) | {Vt.T}, [Xn] |
Load one vector of structures (one register). | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 221 210 20–160 0 0 0 0 15–120 1 1 1 11–10size00 9–5Rn00001 4–0Rt00000 Example
ld1 {v0.16b}, [x1]4c40702020 70 40 4c |
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| ld1 (2 reg) | {Vt.T, Vt2.T}, [Xn] |
Load into two registers. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 221 210 20–160 0 0 0 0 15–121 0 1 0 11–10size00 9–5Rn00010 4–0Rt00000 Example
ld1 {v0.16b, v1.16b}, [x2]4c40a04040 a0 40 4c |
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| ld1 (3 reg) | {Vt..Vt+2.T}, [Xn] |
Load into three registers. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 221 210 20–160 0 0 0 0 15–120 1 1 0 11–10size00 9–5Rn00011 4–0Rt00000 Example
ld1 {v0.16b, v1.16b, v2.16b}, [x3]4c40606060 60 40 4c |
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| ld1 (4 reg) | {Vt..Vt+3.T}, [Xn] |
Load into four registers. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 221 210 20–160 0 0 0 0 15–120 0 1 0 11–10size00 9–5Rn00100 4–0Rt00000 Example
ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x4]4c40208080 20 40 4c |
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| st1 (1 reg) | {Vt.T}, [Xn] |
Store one vector. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 220 210 20–160 0 0 0 0 15–120 1 1 1 11–10size00 9–5Rn00001 4–0Rt00000 Example
st1 {v0.16b}, [x1]4c00702020 70 00 4c |
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| st1 (4 reg) | {Vt..Vt+3.T}, [Xn] |
Store four vectors. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 220 210 20–160 0 0 0 0 15–120 0 1 0 11–10size00 9–5Rn00100 4–0Rt00000 Example
st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x4]4c00208080 20 00 4c |
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| ld2 (mult) | {Vt.T, Vt2.T}, [Xn] |
Load two-element structures, de-interleaved into two registers. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 221 210 20–160 0 0 0 0 15–121 0 0 0 11–10size00 9–5Rn00010 4–0Rt00000 Example
ld2 {v0.16b, v1.16b}, [x2]4c40804040 80 40 4c |
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| st2 (mult) | {Vt.T, Vt2.T}, [Xn] |
Store two-element structures, interleaved. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 220 210 20–160 0 0 0 0 15–121 0 0 0 11–10size00 9–5Rn00010 4–0Rt00000 Example
st2 {v0.16b, v1.16b}, [x2]4c00804040 80 00 4c |
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| ld3 (mult) | {Vt..Vt+2.T}, [Xn] |
Load three-element structures (e.g. RGB), de-interleaved. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 221 210 20–160 0 0 0 0 15–120 1 0 0 11–10size00 9–5Rn00011 4–0Rt00000 Example
ld3 {v0.16b, v1.16b, v2.16b}, [x3]4c40406060 40 40 4c |
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| st3 (mult) | {Vt..Vt+2.T}, [Xn] |
Store three-element structures, interleaved. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 220 210 20–160 0 0 0 0 15–120 1 0 0 11–10size00 9–5Rn00011 4–0Rt00000 Example
st3 {v0.16b, v1.16b, v2.16b}, [x3]4c00406060 40 00 4c |
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| ld4 (mult) | {Vt..Vt+3.T}, [Xn] |
Load four-element structures (e.g. RGBA), de-interleaved. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 221 210 20–160 0 0 0 0 15–120 0 0 0 11–10size00 9–5Rn00100 4–0Rt00000 Example
ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x4]4c40008080 00 40 4c |
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| st4 (mult) | {Vt..Vt+3.T}, [Xn] |
Store four-element structures, interleaved. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 0 220 210 20–160 0 0 0 0 15–120 0 0 0 11–10size00 9–5Rn00100 4–0Rt00000 Example
st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x4]4c00008080 00 00 4c |
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| ld1 (post, reg) | {Vt.T}, [Xn], Xm |
Load and advance Xn by Xm. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 1 221 210 20–16Rm00010 15–120 1 1 1 11–10size00 9–5Rn00001 4–0Rt00000 Example
ld1 {v0.16b}, [x1], x24cc2702020 70 c2 4c |
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| ld1 (post, imm) | {Vt.T}, [Xn], #imm |
Load and advance Xn by the transfer size. | SIMD |
|
310 30Q1 29–230 0 1 1 0 0 1 221 210 20–161 1 1 1 1 15–120 1 1 1 11–10size00 9–5Rn00001 4–0Rt00000 Example
ld1 {v0.16b}, [x1], #164cdf702020 70 df 4c |
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| ld1r | {Vt.T}, [Xn] |
Load one element and replicate it to every lane. | SIMD |
|
310 30Q1 29–230 0 1 1 0 1 0 221 210 20–160 0 0 0 0 15–131 1 0 120 11–10size10 9–5Rn00001 4–0Rt00000 Example
ld1r {v0.4s}, [x1]4d40c82020 c8 40 4d |
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| ld1 (single) | {Vt.S}[i], [Xn] |
Load one 32-bit element into a chosen lane. | SIMD |
|
310 30Q0 29–230 0 1 1 0 1 0 221 210 20–160 0 0 0 0 15–131 0 0 12S1 11–10size00 9–5Rn00001 4–0Rt00000 Example
ld1 {v0.s}[1], [x1]0d40902020 90 40 0d |
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| st1 (single) | {Vt.S}[i], [Xn] |
Store one lane to memory. | SIMD |
|
310 30Q0 29–230 0 1 1 0 1 0 220 210 20–160 0 0 0 0 15–131 0 0 12S1 11–10size00 9–5Rn00001 4–0Rt00000 Example
st1 {v0.s}[1], [x1]0d00902020 90 00 0d |
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| ld2r | {Vt.T, Vt2.T}, [Xn] |
Load a two-element structure and replicate. | SIMD |
|
310 30Q1 29–230 0 1 1 0 1 0 221 211 20–160 0 0 0 0 15–131 1 0 120 11–10size10 9–5Rn00001 4–0Rt00000 Example
ld2r {v0.4s, v1.4s}, [x1]4d60c82020 c8 60 4d |
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| SIMD scalar | |||
| add (scalar) | Dd, Dn, Dm |
Scalar 64-bit integer add in the SIMD unit. | SIMD |
|
310 301 290 28–241 1 1 1 0 23–221 1 211 20–16Rm00010 15–111 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
add d0, d1, d25ee2842020 84 e2 5e |
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| sub (scalar) | Dd, Dn, Dm |
Scalar 64-bit integer subtract. | SIMD |
|
310 301 291 28–241 1 1 1 0 23–221 1 211 20–16Rm00010 15–111 0 0 0 0 101 9–5Rn00001 4–0Rd00000 Example
sub d0, d1, d27ee2842020 84 e2 7e |
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| cmeq (scalar) | Dd, Dn, Dm |
Scalar compare equal. | SIMD |
|
310 301 291 28–241 1 1 1 0 23–221 1 211 20–16Rm00010 15–111 0 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
cmeq d0, d1, d27ee28c2020 8c e2 7e |
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| sqadd (scalar) | Bd, Bn, Bm |
Scalar saturating add (element size from the register letter). | SIMD |
|
310 301 290 28–241 1 1 1 0 23–22size00 211 20–16Rm00010 15–110 0 0 0 1 101 9–5Rn00001 4–0Rd00000 Example
sqadd b0, b1, b25e220c2020 0c 22 5e |
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| sqdmulh (scalar) | Hd, Hn, Hm |
Scalar saturating doubling multiply high. | SIMD |
|
310 301 290 28–241 1 1 1 0 23–22size01 211 20–16Rm00010 15–111 0 1 1 0 101 9–5Rn00001 4–0Rd00000 Example
sqdmulh h0, h1, h25e62b42020 b4 62 5e |
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| abs (scalar) | Dd, Dn |
Scalar absolute value. | SIMD |
|
310 301 290 28–241 1 1 1 0 23–221 1 21–171 0 0 0 0 16–120 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
abs d0, d15ee0b82020 b8 e0 5e |
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| neg (scalar) | Dd, Dn |
Scalar negate. | SIMD |
|
310 301 291 28–241 1 1 1 0 23–221 1 21–171 0 0 0 0 16–120 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
neg d0, d17ee0b82020 b8 e0 7e |
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| fabd (scalar) | Sd, Sn, Sm |
Scalar FP absolute difference. | SIMD |
|
310 301 291 28–241 1 1 1 0 231 22sz0 211 20–16Rm00010 15–111 1 0 1 0 101 9–5Rn00001 4–0Rd00000 Example
fabd s0, s1, s27ea2d42020 d4 a2 7e |
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| fcmeq (scalar) | Sd, Sn, Sm |
Scalar FP compare equal (result all-ones/zero). | SIMD |
|
310 301 290 28–241 1 1 1 0 230 22sz0 211 20–16Rm00010 15–111 1 1 0 0 101 9–5Rn00001 4–0Rd00000 Example
fcmeq s0, s1, s25e22e42020 e4 22 5e |
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| frecpe (scalar) | Sd, Sn |
Scalar FP reciprocal estimate. | SIMD |
|
310 301 290 28–241 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 1 0 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
frecpe s0, s15ea1d82020 d8 a1 5e |
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| frecps (scalar) | Sd, Sn, Sm |
Scalar FP reciprocal step. | SIMD |
|
310 301 290 28–241 1 1 1 0 230 22sz0 211 20–16Rm00010 15–111 1 1 1 1 101 9–5Rn00001 4–0Rd00000 Example
frecps s0, s1, s25e22fc2020 fc 22 5e |
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| fcvtzs (scalar simd) | Sd, Sn |
Scalar FP to signed int, toward zero (SIMD form). | SIMD |
|
310 301 290 28–241 1 1 1 0 231 22sz0 21–171 0 0 0 0 16–121 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
fcvtzs s0, s15ea1b82020 b8 a1 5e |
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| dup (scalar elem) | Vd, Vn.Ts[i] |
Duplicate one element into a scalar register. | SIMD |
|
310 301 290 28–211 1 1 1 0 0 0 0 20–16imm511000 15–100 0 0 0 0 1 9–5Rn00001 4–0Rd00000 Example
dup d0, v1.d[1]5e18042020 04 18 5e |
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| sqxtn (scalar) | Bd, Hn |
Scalar saturating extract narrow. | SIMD |
|
310 301 290 28–241 1 1 1 0 23–22size00 21–171 0 0 0 0 16–121 0 1 0 0 11–101 0 9–5Rn00001 4–0Rd00000 Example
sqxtn b0, h15e21482020 48 21 5e |
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| addp (scalar) | Dd, Vn.2D |
Add the two lanes of a 2D vector into a scalar. | SIMD |
|
310 301 290 28–241 1 1 1 0 23–221 1 21–171 1 0 0 0 16–121 1 0 1 1 11–101 0 9–5Rn00001 4–0Rd00000 Example
addp d0, v1.2d5ef1b82020 b8 f1 5e |
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No instruction matches this filter.