RISC-V Instruction Set Reference

A compact reference for the RISC-V instructions you meet when reversing RV64 binaries, firmware or shellcode: base integer, the G extensions (M, A, F, D, Zicsr, Zifencei), C, the B bit-manipulation extensions (Zba, Zbb, Zbs) and the privileged instructions. Every encoding below is checked against the LLVM assembler. The vector extension (V) is not covered.

Registers
Instruction formats
Opcode map
Pseudo-instructions
Common CSRs
Instructions
Calling convention

Registers

Register	ABI name	Role	Saved by
x0	zero	Hard-wired zero. Writes are ignored.	—
x1	ra	Return address	Caller
x2	sp	Stack pointer (16-byte aligned)	Callee
x3	gp	Global pointer (linker relaxation)	—
x4	tp	Thread pointer (TLS)	—
x5–x7	t0–t2	Temporaries (t0 is the alternate link register)	Caller
x8	s0 / fp	Saved register / frame pointer	Callee
x9	s1	Saved register	Callee
x10–x11	a0–a1	Arguments / return values	Caller
x12–x17	a2–a7	Arguments (a7 = syscall number on Linux)	Caller
x18–x27	s2–s11	Saved registers	Callee
x28–x31	t3–t6	Temporaries	Caller
f0–f7	ft0–ft7	FP temporaries	Caller
f8–f9	fs0–fs1	FP saved registers	Callee
f10–f11	fa0–fa1	FP arguments / return values	Caller
f12–f17	fa2–fa7	FP arguments	Caller
f18–f27	fs2–fs11	FP saved registers	Callee
f28–f31	ft8–ft11	FP temporaries	Caller

There are no condition flags: comparisons write a register (slt) or branch directly (blt). pc is not a general purpose register. XLEN is 32 on RV32 and 64 on RV64. On RV64, 32-bit results (*w instructions, lw) are always sign-extended to 64 bits, even for unsigned int. Compressed instructions with a ' register field (rd', rs1', rs2') can only use x8–x15 (s0, s1, a0–a5).

Instruction formats

Instructions are 32 bits, little endian, 4-byte aligned (2-byte aligned with C). If the two low bits are not 11, the instruction is a 16-bit compressed one. rd, rs1 and rs2 always sit at the same position, and the immediate sign bit is always bit 31, so decoding is cheap.

R	31–25funct7 24–20rs2 19–15rs1 14–12funct3 11–7rd 6–0opcode
I	31–20imm[11:0] 19–15rs1 14–12funct3 11–7rd 6–0opcode
S	31–25imm[11:5] 24–20rs2 19–15rs1 14–12funct3 11–7imm[4:0] 6–0opcode
B	31–25imm[12\|10:5] 24–20rs2 19–15rs1 14–12funct3 11–7imm[4:1\|11] 6–0opcode
U	31–12imm[31:12] 11–7rd 6–0opcode
J	31–12imm[20\|10:1\|11\|19:12] 11–7rd 6–0opcode
R4	31–27rs3 26–25fmt 24–20rs2 19–15rs1 14–12funct3 11–7rd 6–0opcode

Opcode map (inst[6:0], low bits always 11)

inst[4:2] → inst[6:5] ↓	000	001	010	011	100	101	110	111
00	LOAD	LOAD-FP	custom-0	MISC-MEM	OP-IMM	AUIPC	OP-IMM-32	48-bit
01	STORE	STORE-FP	custom-1	AMO	OP	LUI	OP-32	64-bit
10	MADD	MSUB	NMSUB	NMADD	OP-FP	OP-V	custom-2	48-bit
11	BRANCH	JALR	reserved	JAL	SYSTEM	OP-VE	custom-3	≥80-bit

Pseudo-instructions (what disassemblers show vs. what is encoded)

Pseudo-instruction	Real instruction(s)
nop	addi x0, x0, 0
li rd, imm	lui/addi(w)/slli sequence chosen by the assembler
la rd, sym	auipc rd, %pcrel_hi(sym) ; addi rd, rd, %pcrel_lo
mv rd, rs	addi rd, rs, 0
not rd, rs	xori rd, rs, -1
neg rd, rs	sub rd, x0, rs
negw rd, rs	subw rd, x0, rs
sext.w rd, rs	addiw rd, rs, 0
zext.b rd, rs	andi rd, rs, 255
seqz rd, rs	sltiu rd, rs, 1
snez rd, rs	sltu rd, x0, rs
sltz rd, rs	slt rd, rs, x0
sgtz rd, rs	slt rd, x0, rs
beqz / bnez rs, off	beq / bne rs, x0, off
blez rs, off	bge x0, rs, off
bgez / bltz rs, off	bge / blt rs, x0, off
bgtz rs, off	blt x0, rs, off
bgt / ble / bgtu / bleu a, b, off	blt / bge / bltu / bgeu b, a, off
j off	jal x0, off
jal off	jal ra, off
jr rs	jalr x0, 0(rs)
jalr rs	jalr ra, 0(rs)
ret	jalr x0, 0(ra)
call sym	auipc ra, %pcrel_hi(sym) ; jalr ra, %pcrel_lo(ra)
tail sym	auipc t1, %pcrel_hi(sym) ; jalr x0, %pcrel_lo(t1)
csrr rd, csr	csrrs rd, csr, x0
csrw / csrs / csrc csr, rs	csrrw / csrrs / csrrc x0, csr, rs
rdcycle / rdtime / rdinstret rd	csrrs rd, cycle / time / instret, x0
fmv.s / fabs.s / fneg.s rd, rs	fsgnj.s / fsgnjx.s / fsgnjn.s rd, rs, rs

Common CSRs

Number	Name	Purpose
0x001	fflags	FP accrued exceptions
0x002	frm	FP dynamic rounding mode
0x003	fcsr	frm + fflags
0xC00	cycle	Cycle counter (user read-only)
0xC01	time	Real-time counter
0xC02	instret	Instructions retired
0x100	sstatus	Supervisor status (SIE, SPIE, SPP, SUM, MXR...)
0x104	sie	Supervisor interrupt enable
0x105	stvec	Supervisor trap vector base
0x140	sscratch	Supervisor scratch
0x141	sepc	Supervisor exception PC
0x142	scause	Supervisor trap cause
0x143	stval	Supervisor bad address / instruction
0x144	sip	Supervisor interrupt pending
0x180	satp	Address translation: MODE (Sv39/48/57), ASID, root PPN
0x300	mstatus	Machine status (MIE, MPIE, MPP, MPRV...)
0x301	misa	ISA and extensions
0x302	medeleg	Exception delegation to S-mode
0x303	mideleg	Interrupt delegation to S-mode
0x304	mie	Machine interrupt enable
0x305	mtvec	Machine trap vector base
0x340	mscratch	Machine scratch
0x341	mepc	Machine exception PC
0x342	mcause	Machine trap cause
0x343	mtval	Machine bad address / instruction
0x344	mip	Machine interrupt pending
0xF14	mhartid	Hart ID

The two top bits of the CSR number say whether it is read-only (11), and bits 9:8 give the lowest privilege allowed to access it (00 = U, 01 = S, 11 = M).

Instructions (239 entries)

Mnemonic	Syntax	Description	Ext.
Integer computation
lui	`rd, imm20`	Load upper immediate: `rd = sext(imm20 << 12)`. Low 12 bits are zero.	I
31–12imm[31:12]00010010001101000101 11–7rd01010 6–00 1 1 0 1 1 1 Pair with `addi` to build any 32-bit constant. If bit 11 of the low part is set, the assembler rounds the upper part up by one because `addi` sign-extends. Example`lui a0, 0x12345`1234553737 55 34 12
auipc	`rd, imm20`	Add upper immediate to PC: `rd = pc + sext(imm20 << 12)`.	I
31–12imm[31:12]00000000000000000001 11–7rd00101 6–00 0 1 0 1 1 1 Base of all PC-relative addressing (`la`, `call`, GOT accesses). Useful in shellcode to find where you are without a call. Example`auipc t0, 0x1`0000129797 12 00 00
addi	`rd, rs1, imm12`	`rd = rs1 + sext(imm12)`. Overflow is ignored.	I
31–20imm[11:0]111111010110 19–15rs101011 14–120 0 0 11–7rd01010 6–00 0 1 0 0 1 1 `addi x0, x0, 0` is the canonical `nop` (0x00000013). `mv rd, rs` is `addi rd, rs, 0`. Example`addi a0, a1, -42`fd65851313 85 65 fd
slti	`rd, rs1, imm12`	Set rd to 1 if rs1 < sext(imm12) (signed), else 0.	I
31–20imm[11:0]000000001010 19–15rs101011 14–120 1 0 11–7rd01010 6–00 0 1 0 0 1 1 Example`slti a0, a1, 10`00a5a51313 a5 a5 00
sltiu	`rd, rs1, imm12`	Set rd to 1 if rs1 < sext(imm12) (unsigned), else 0.	I
31–20imm[11:0]000000000001 19–15rs101011 14–120 1 1 11–7rd01010 6–00 0 1 0 0 1 1 `seqz rd, rs` is `sltiu rd, rs, 1`. Example`sltiu a0, a1, 1`0015b51313 b5 15 00
xori	`rd, rs1, imm12`	`rd = rs1 ^ sext(imm12)`.	I
31–20imm[11:0]111111111111 19–15rs101011 14–121 0 0 11–7rd01010 6–00 0 1 0 0 1 1 `not rd, rs` is `xori rd, rs, -1`. Example`xori a0, a1, -1`fff5c51313 c5 f5 ff
ori	`rd, rs1, imm12`	`rd = rs1 \| sext(imm12)`.	I
31–20imm[11:0]000011111111 19–15rs101011 14–121 1 0 11–7rd01010 6–00 0 1 0 0 1 1 Example`ori a0, a1, 0xff`0ff5e51313 e5 f5 0f
andi	`rd, rs1, imm12`	`rd = rs1 & sext(imm12)`.	I
31–20imm[11:0]000011111111 19–15rs101011 14–121 1 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`andi a0, a1, 0xff`0ff5f51313 f5 f5 0f
slli	`rd, rs1, shamt`	Logical shift left by an immediate (0–63 on RV64, 0–31 on RV32).	I
31–260 0 0 0 0 0 25–20shamt000011 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`slli a0, a1, 3`0035951313 95 35 00
srli	`rd, rs1, shamt`	Logical shift right by an immediate (zeros shifted in).	I
31–260 0 0 0 0 0 25–20shamt000011 19–15rs101011 14–121 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`srli a0, a1, 3`0035d51313 d5 35 00
srai	`rd, rs1, shamt`	Arithmetic shift right by an immediate (sign bit shifted in).	I
31–260 1 0 0 0 0 25–20shamt000011 19–15rs101011 14–121 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`srai a0, a1, 3`4035d51313 d5 35 40
add	`rd, rs1, rs2`	`rd = rs1 + rs2`.	I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`add a0, a1, a2`00c5853333 85 c5 00
sub	`rd, rs1, rs2`	`rd = rs1 - rs2`.	I
31–250 1 0 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–00 1 1 0 0 1 1 `neg rd, rs` is `sub rd, x0, rs`. Example`sub a0, a1, a2`40c5853333 85 c5 40
sll	`rd, rs1, rs2`	Logical shift left by the low 6 (RV64) or 5 (RV32) bits of rs2.	I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`sll a0, a1, a2`00c5953333 95 c5 00
slt	`rd, rs1, rs2`	Set rd to 1 if rs1 < rs2 (signed), else 0.	I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`slt a0, a1, a2`00c5a53333 a5 c5 00
sltu	`rd, rs1, rs2`	Set rd to 1 if rs1 < rs2 (unsigned), else 0.	I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 1 0 0 1 1 `snez rd, rs` is `sltu rd, x0, rs`. Example`sltu a0, a1, a2`00c5b53333 b5 c5 00
xor	`rd, rs1, rs2`	`rd = rs1 ^ rs2`.	I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`xor a0, a1, a2`00c5c53333 c5 c5 00
srl	`rd, rs1, rs2`	Logical shift right by the low bits of rs2.	I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`srl a0, a1, a2`00c5d53333 d5 c5 00
sra	`rd, rs1, rs2`	Arithmetic shift right by the low bits of rs2.	I
31–250 1 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`sra a0, a1, a2`40c5d53333 d5 c5 40
or	`rd, rs1, rs2`	`rd = rs1 \| rs2`.	I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 1 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`or a0, a1, a2`00c5e53333 e5 c5 00
and	`rd, rs1, rs2`	`rd = rs1 & rs2`.	I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 1 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`and a0, a1, a2`00c5f53333 f5 c5 00
RV64 word operations
addiw	`rd, rs1, imm12`	32-bit add immediate, result sign-extended to 64 bits.	RV64I
31–20imm[11:0]000000000001 19–15rs101011 14–120 0 0 11–7rd01010 6–00 0 1 1 0 1 1 `sext.w rd, rs` is `addiw rd, rs, 0`. Very common in compiled code that handles `int`. Example`addiw a0, a1, 1`0015851b1b 85 15 00
slliw	`rd, rs1, shamt`	32-bit shift left by immediate, result sign-extended.	RV64I
31–250 0 0 0 0 0 0 24–20shamt00011 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 1 0 1 1 Example`slliw a0, a1, 3`0035951b1b 95 35 00
srliw	`rd, rs1, shamt`	32-bit logical shift right by immediate, result sign-extended.	RV64I
31–250 0 0 0 0 0 0 24–20shamt00011 19–15rs101011 14–121 0 1 11–7rd01010 6–00 0 1 1 0 1 1 Example`srliw a0, a1, 3`0035d51b1b d5 35 00
sraiw	`rd, rs1, shamt`	32-bit arithmetic shift right by immediate, result sign-extended.	RV64I
31–250 1 0 0 0 0 0 24–20shamt00011 19–15rs101011 14–121 0 1 11–7rd01010 6–00 0 1 1 0 1 1 Example`sraiw a0, a1, 3`4035d51b1b d5 35 40
addw	`rd, rs1, rs2`	32-bit add, result sign-extended.	RV64I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–00 1 1 1 0 1 1 Example`addw a0, a1, a2`00c5853b3b 85 c5 00
subw	`rd, rs1, rs2`	32-bit subtract, result sign-extended.	RV64I
31–250 1 0 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–00 1 1 1 0 1 1 Example`subw a0, a1, a2`40c5853b3b 85 c5 40
sllw	`rd, rs1, rs2`	32-bit shift left by the low 5 bits of rs2, result sign-extended.	RV64I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–00 1 1 1 0 1 1 Example`sllw a0, a1, a2`00c5953b3b 95 c5 00
srlw	`rd, rs1, rs2`	32-bit logical shift right, result sign-extended.	RV64I
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 1 0 1 1 Example`srlw a0, a1, a2`00c5d53b3b d5 c5 00
sraw	`rd, rs1, rs2`	32-bit arithmetic shift right, result sign-extended.	RV64I
31–250 1 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 1 0 1 1 Example`sraw a0, a1, a2`40c5d53b3b d5 c5 40
Loads and stores
lb	`rd, imm12(rs1)`	Load a byte, sign-extended.	I
31–20imm[11:0]000000000100 19–15rs100010 14–120 0 0 11–7rd01010 6–00 0 0 0 0 1 1 Example`lb a0, 4(sp)`0041050303 05 41 00
lh	`rd, imm12(rs1)`	Load a halfword, sign-extended.	I
31–20imm[11:0]000000000100 19–15rs100010 14–120 0 1 11–7rd01010 6–00 0 0 0 0 1 1 Example`lh a0, 4(sp)`0041150303 15 41 00
lw	`rd, imm12(rs1)`	Load a word, sign-extended (on RV64).	I
31–20imm[11:0]000000000100 19–15rs100010 14–120 1 0 11–7rd01010 6–00 0 0 0 0 1 1 Example`lw a0, 4(sp)`0041250303 25 41 00
ld	`rd, imm12(rs1)`	Load a doubleword.	RV64I
31–20imm[11:0]000000001000 19–15rs100010 14–120 1 1 11–7rd01010 6–00 0 0 0 0 1 1 Example`ld a0, 8(sp)`0081350303 35 81 00
lbu	`rd, imm12(rs1)`	Load a byte, zero-extended.	I
31–20imm[11:0]000000000100 19–15rs100010 14–121 0 0 11–7rd01010 6–00 0 0 0 0 1 1 Example`lbu a0, 4(sp)`0041450303 45 41 00
lhu	`rd, imm12(rs1)`	Load a halfword, zero-extended.	I
31–20imm[11:0]000000000100 19–15rs100010 14–121 0 1 11–7rd01010 6–00 0 0 0 0 1 1 Example`lhu a0, 4(sp)`0041550303 55 41 00
lwu	`rd, imm12(rs1)`	Load a word, zero-extended.	RV64I
31–20imm[11:0]000000000100 19–15rs100010 14–121 1 0 11–7rd01010 6–00 0 0 0 0 1 1 Example`lwu a0, 4(sp)`0041650303 65 41 00
sb	`rs2, imm12(rs1)`	Store the low byte of rs2.	I
31–25imm[11:5]0000000 24–20rs201010 19–15rs100010 14–120 0 0 11–7imm[4:0]00100 6–00 1 0 0 0 1 1 Example`sb a0, 4(sp)`00a1022323 02 a1 00
sh	`rs2, imm12(rs1)`	Store the low halfword of rs2.	I
31–25imm[11:5]0000000 24–20rs201010 19–15rs100010 14–120 0 1 11–7imm[4:0]00100 6–00 1 0 0 0 1 1 Example`sh a0, 4(sp)`00a1122323 12 a1 00
sw	`rs2, imm12(rs1)`	Store the low word of rs2.	I
31–25imm[11:5]0000000 24–20rs201010 19–15rs100010 14–120 1 0 11–7imm[4:0]00100 6–00 1 0 0 0 1 1 Example`sw a0, 4(sp)`00a1222323 22 a1 00
sd	`rs2, imm12(rs1)`	Store a doubleword.	RV64I
31–25imm[11:5]0000000 24–20rs200001 19–15rs100010 14–120 1 1 11–7imm[4:0]01000 6–00 1 0 0 0 1 1 Example`sd ra, 8(sp)`0011342323 34 11 00
Control transfer
jal	`rd, offset`	Jump to `pc + offset` (±1 MiB) and write the return address `pc + 4` to rd.	I
31–12imm[20\|10:1\|11\|19:12]00000000000100000000 11–7rd00001 6–01 1 0 1 1 1 1 `j off` is `jal x0, off`. `jal off` uses `ra`. The immediate bits are scrambled so that the sign bit is always inst[31]. Example`jal ra, 2048`001000efef 00 10 00
jalr	`rd, imm12(rs1)`	Jump to `(rs1 + sext(imm12)) & ~1` and write `pc + 4` to rd.	I
31–20imm[11:0]000000000000 19–15rs100101 14–120 0 0 11–7rd00001 6–01 1 0 0 1 1 1 `ret` is `jalr x0, 0(ra)` (0x00008067). `jr rs` is `jalr x0, 0(rs)`. With `auipc` it reaches ±2 GiB (`call`, `tail`). Example`jalr ra, 0(t0)`000280e7e7 80 02 00
beq	`rs1, rs2, offset`	Branch if rs1 == rs2 (±4 KiB).	I
31–25imm[12\|10:5]0000000 24–20rs201011 19–15rs101010 14–120 0 0 11–7imm[4:1\|11]10000 6–01 1 0 0 0 1 1 `beqz rs, off` is `beq rs, x0, off`. Example`beq a0, a1, 16`00b5086363 08 b5 00
bne	`rs1, rs2, offset`	Branch if rs1 != rs2.	I
31–25imm[12\|10:5]0000000 24–20rs201011 19–15rs101010 14–120 0 1 11–7imm[4:1\|11]10000 6–01 1 0 0 0 1 1 `bnez rs, off` is `bne rs, x0, off`. Example`bne a0, a1, 16`00b5186363 18 b5 00
blt	`rs1, rs2, offset`	Branch if rs1 < rs2 (signed).	I
31–25imm[12\|10:5]0000000 24–20rs201011 19–15rs101010 14–121 0 0 11–7imm[4:1\|11]10000 6–01 1 0 0 0 1 1 `bgt a, b` is `blt b, a`. Example`blt a0, a1, 16`00b5486363 48 b5 00
bge	`rs1, rs2, offset`	Branch if rs1 ≥ rs2 (signed).	I
31–25imm[12\|10:5]0000000 24–20rs201011 19–15rs101010 14–121 0 1 11–7imm[4:1\|11]10000 6–01 1 0 0 0 1 1 `ble a, b` is `bge b, a`. Example`bge a0, a1, 16`00b5586363 58 b5 00
bltu	`rs1, rs2, offset`	Branch if rs1 < rs2 (unsigned).	I
31–25imm[12\|10:5]0000000 24–20rs201011 19–15rs101010 14–121 1 0 11–7imm[4:1\|11]10000 6–01 1 0 0 0 1 1 Example`bltu a0, a1, 16`00b5686363 68 b5 00
bgeu	`rs1, rs2, offset`	Branch if rs1 ≥ rs2 (unsigned).	I
31–25imm[12\|10:5]0000000 24–20rs201011 19–15rs101010 14–121 1 1 11–7imm[4:1\|11]10000 6–01 1 0 0 0 1 1 Example`bgeu a0, a1, 16`00b5786363 78 b5 00
Synchronization and environment
fence	`pred, succ`	Memory ordering: no access in the succ set (any of I, O, R, W) is observed before an access in the pred set.	I
31–28fm0000 27–24pred0011 23–20succ0011 19–15rs100000 14–120 0 0 11–7rd00000 6–00 0 0 1 1 1 1 Example`fence rw, rw`0330000f0f 00 30 03
fence.tso		Total-store-ordering fence: orders RW→RW except W→R.	I
31–281 0 0 0 27–240 0 1 1 23–200 0 1 1 19–150 0 0 0 0 14–120 0 0 11–70 0 0 0 0 6–00 0 0 1 1 1 1 Example`fence.tso`8330000f0f 00 30 83
pause		Spin-loop hint, encoded as a fence with pred=W and succ=0.	Zihintpause
31–280 0 0 0 27–240 0 0 1 23–200 0 0 0 19–150 0 0 0 0 14–120 0 0 11–70 0 0 0 0 6–00 0 0 1 1 1 1 Example`pause`0100000f0f 00 00 01
fence.i		Synchronize the instruction stream with prior stores of the same hart.	Zifencei
31–20imm[11:0]000000000000 19–15rs100000 14–120 0 1 11–7rd00000 6–00 0 0 1 1 1 1 Needed by self-modifying code and JITs after writing instructions. Other harts need a remote fence (on Linux, `riscv_flush_icache` syscall). Example`fence.i`0000100f0f 10 00 00
ecall		Environment call: trap to the next privilege level (system call).	I
31–200 0 0 0 0 0 0 0 0 0 0 0 19–150 0 0 0 0 14–120 0 0 11–70 0 0 0 0 6–01 1 1 0 0 1 1 Linux: syscall number in `a7`, arguments in `a0`–`a5`, result in `a0`. Encoding 0x00000073. Example`ecall`0000007373 00 00 00
ebreak		Breakpoint trap, used by debuggers.	I
31–200 0 0 0 0 0 0 0 0 0 0 1 19–150 0 0 0 0 14–120 0 0 11–70 0 0 0 0 6–01 1 1 0 0 1 1 Example`ebreak`0010007373 00 10 00
Control and status registers
csrrw	`rd, csr, rs1`	Atomically swap: rd = csr, csr = rs1. The CSR is not read if rd is x0.	Zicsr
31–20csr001101000000 19–15rs101011 14–120 0 1 11–7rd01010 6–01 1 1 0 0 1 1 `csrw csr, rs` is `csrrw x0, csr, rs`. Example`csrrw a0, mscratch, a1`3405957373 95 05 34
csrrs	`rd, csr, rs1`	Read and set bits: rd = csr, csr \|= rs1. No write if rs1 is x0.	Zicsr
31–20csr001100000000 19–15rs101011 14–120 1 0 11–7rd01010 6–01 1 1 0 0 1 1 `csrr rd, csr` is `csrrs rd, csr, x0`. `rdcycle`, `rdtime` and `rdinstret` also use it. Example`csrrs a0, mstatus, a1`3005a57373 a5 05 30
csrrc	`rd, csr, rs1`	Read and clear bits: rd = csr, csr &= ~rs1.	Zicsr
31–20csr001100000100 19–15rs101011 14–120 1 1 11–7rd01010 6–01 1 1 0 0 1 1 Example`csrrc a0, mie, a1`3045b57373 b5 45 30
csrrwi	`rd, csr, uimm5`	Like csrrw with a 5-bit zero-extended immediate.	Zicsr
31–20csr000000000011 19–15uimm00001 14–121 0 1 11–7rd01010 6–01 1 1 0 0 1 1 Example`csrrwi a0, fcsr, 1`0030d57373 d5 30 00
csrrsi	`rd, csr, uimm5`	Like csrrs with a 5-bit immediate.	Zicsr
31–20csr001100000000 19–15uimm01000 14–121 1 0 11–7rd01010 6–01 1 1 0 0 1 1 `csrsi mstatus, 8` sets MIE (enables machine interrupts). Example`csrrsi a0, mstatus, 8`3004657373 65 04 30
csrrci	`rd, csr, uimm5`	Like csrrc with a 5-bit immediate.	Zicsr
31–20csr001100000000 19–15uimm01000 14–121 1 1 11–7rd01010 6–01 1 1 0 0 1 1 Example`csrrci a0, mstatus, 8`3004757373 75 04 30
Multiply and divide
mul	`rd, rs1, rs2`	Low XLEN bits of rs1 × rs2.	M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`mul a0, a1, a2`02c5853333 85 c5 02
mulh	`rd, rs1, rs2`	High XLEN bits of signed × signed.	M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`mulh a0, a1, a2`02c5953333 95 c5 02
mulhsu	`rd, rs1, rs2`	High XLEN bits of signed rs1 × unsigned rs2.	M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`mulhsu a0, a1, a2`02c5a53333 a5 c5 02
mulhu	`rd, rs1, rs2`	High XLEN bits of unsigned × unsigned.	M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`mulhu a0, a1, a2`02c5b53333 b5 c5 02
div	`rd, rs1, rs2`	Signed division, rounds toward zero. x/0 = -1; MIN/-1 = MIN (no trap).	M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–121 0 0 11–7rd01010 6–00 1 1 0 0 1 1 Division never traps: compilers emit an explicit check before calling it when the language requires one. Example`div a0, a1, a2`02c5c53333 c5 c5 02
divu	`rd, rs1, rs2`	Unsigned division. x/0 = 2^XLEN-1.	M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`divu a0, a1, a2`02c5d53333 d5 c5 02
rem	`rd, rs1, rs2`	Signed remainder (sign of the dividend). x%0 = x.	M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–121 1 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`rem a0, a1, a2`02c5e53333 e5 c5 02
remu	`rd, rs1, rs2`	Unsigned remainder. x%0 = x.	M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–121 1 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`remu a0, a1, a2`02c5f53333 f5 c5 02
mulw	`rd, rs1, rs2`	32-bit multiply, low 32 bits sign-extended.	RV64M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–00 1 1 1 0 1 1 Example`mulw a0, a1, a2`02c5853b3b 85 c5 02
divw	`rd, rs1, rs2`	32-bit signed division, result sign-extended.	RV64M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–121 0 0 11–7rd01010 6–00 1 1 1 0 1 1 Example`divw a0, a1, a2`02c5c53b3b c5 c5 02
divuw	`rd, rs1, rs2`	32-bit unsigned division, result sign-extended.	RV64M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 1 0 1 1 Example`divuw a0, a1, a2`02c5d53b3b d5 c5 02
remw	`rd, rs1, rs2`	32-bit signed remainder, result sign-extended.	RV64M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–121 1 0 11–7rd01010 6–00 1 1 1 0 1 1 Example`remw a0, a1, a2`02c5e53b3b e5 c5 02
remuw	`rd, rs1, rs2`	32-bit unsigned remainder, result sign-extended.	RV64M
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–121 1 1 11–7rd01010 6–00 1 1 1 0 1 1 Example`remuw a0, a1, a2`02c5f53b3b f5 c5 02
Atomics
lr.w	`rd, (rs1)`	Load-reserved: load and register a reservation on the address.	A
31–270 0 0 1 0 26aq1 25rl0 24–200 0 0 0 0 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 The `.aq` / `.rl` / `.aqrl` suffixes set the acquire and release bits. Example`lr.w.aq a0, (a1)`1405a52f2f a5 05 14
sc.w	`rd, rs2, (rs1)`	Store-conditional: store if the reservation is still valid; rd = 0 on success, non-zero on failure.	A
31–270 0 0 1 1 26aq0 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 A typical CAS loop is `lr`, compare, `sc`, `bnez` back. Example`sc.w.rl a0, a2, (a1)`1ac5a52f2f a5 c5 1a
amoswap.w	`rd, rs2, (rs1)`	Atomically swap rs2 with memory; rd gets the old value.	A
31–270 0 0 0 1 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoswap.w.aqrl a0, a2, (a1)`0ec5a52f2f a5 c5 0e
amoadd.w	`rd, rs2, (rs1)`	Atomic 32-bit add; rd gets the old value.	A
31–270 0 0 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoadd.w.aqrl a0, a2, (a1)`06c5a52f2f a5 c5 06
amoxor.w	`rd, rs2, (rs1)`	Atomic 32-bit XOR; rd gets the old value.	A
31–270 0 1 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoxor.w.aqrl a0, a2, (a1)`26c5a52f2f a5 c5 26
amoand.w	`rd, rs2, (rs1)`	Atomic 32-bit AND; rd gets the old value.	A
31–270 1 1 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoand.w.aqrl a0, a2, (a1)`66c5a52f2f a5 c5 66
amoor.w	`rd, rs2, (rs1)`	Atomic 32-bit OR; rd gets the old value.	A
31–270 1 0 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoor.w.aqrl a0, a2, (a1)`46c5a52f2f a5 c5 46
amomin.w	`rd, rs2, (rs1)`	Atomic 32-bit signed minimum; rd gets the old value.	A
31–271 0 0 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 Example`amomin.w.aqrl a0, a2, (a1)`86c5a52f2f a5 c5 86
amomax.w	`rd, rs2, (rs1)`	Atomic 32-bit signed maximum; rd gets the old value.	A
31–271 0 1 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 Example`amomax.w.aqrl a0, a2, (a1)`a6c5a52f2f a5 c5 a6
amominu.w	`rd, rs2, (rs1)`	Atomic 32-bit unsigned minimum; rd gets the old value.	A
31–271 1 0 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 Example`amominu.w.aqrl a0, a2, (a1)`c6c5a52f2f a5 c5 c6
amomaxu.w	`rd, rs2, (rs1)`	Atomic 32-bit unsigned maximum; rd gets the old value.	A
31–271 1 1 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 0 1 1 1 1 Example`amomaxu.w.aqrl a0, a2, (a1)`e6c5a52f2f a5 c5 e6
lr.d	`rd, (rs1)`	Load-reserved: load and register a reservation on the address.	RV64A
31–270 0 0 1 0 26aq1 25rl0 24–200 0 0 0 0 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`lr.d.aq a0, (a1)`1405b52f2f b5 05 14
sc.d	`rd, rs2, (rs1)`	Store-conditional: store if the reservation is still valid; rd = 0 on success, non-zero on failure.	RV64A
31–270 0 0 1 1 26aq0 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`sc.d.rl a0, a2, (a1)`1ac5b52f2f b5 c5 1a
amoswap.d	`rd, rs2, (rs1)`	Atomically swap rs2 with memory; rd gets the old value.	RV64A
31–270 0 0 0 1 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoswap.d.aqrl a0, a2, (a1)`0ec5b52f2f b5 c5 0e
amoadd.d	`rd, rs2, (rs1)`	Atomic 64-bit add; rd gets the old value.	RV64A
31–270 0 0 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoadd.d.aqrl a0, a2, (a1)`06c5b52f2f b5 c5 06
amoxor.d	`rd, rs2, (rs1)`	Atomic 64-bit XOR; rd gets the old value.	RV64A
31–270 0 1 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoxor.d.aqrl a0, a2, (a1)`26c5b52f2f b5 c5 26
amoand.d	`rd, rs2, (rs1)`	Atomic 64-bit AND; rd gets the old value.	RV64A
31–270 1 1 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoand.d.aqrl a0, a2, (a1)`66c5b52f2f b5 c5 66
amoor.d	`rd, rs2, (rs1)`	Atomic 64-bit OR; rd gets the old value.	RV64A
31–270 1 0 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`amoor.d.aqrl a0, a2, (a1)`46c5b52f2f b5 c5 46
amomin.d	`rd, rs2, (rs1)`	Atomic 64-bit signed minimum; rd gets the old value.	RV64A
31–271 0 0 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`amomin.d.aqrl a0, a2, (a1)`86c5b52f2f b5 c5 86
amomax.d	`rd, rs2, (rs1)`	Atomic 64-bit signed maximum; rd gets the old value.	RV64A
31–271 0 1 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`amomax.d.aqrl a0, a2, (a1)`a6c5b52f2f b5 c5 a6
amominu.d	`rd, rs2, (rs1)`	Atomic 64-bit unsigned minimum; rd gets the old value.	RV64A
31–271 1 0 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`amominu.d.aqrl a0, a2, (a1)`c6c5b52f2f b5 c5 c6
amomaxu.d	`rd, rs2, (rs1)`	Atomic 64-bit unsigned maximum; rd gets the old value.	RV64A
31–271 1 1 0 0 26aq1 25rl1 24–20rs201100 19–15rs101011 14–120 1 1 11–7rd01010 6–00 1 0 1 1 1 1 Example`amomaxu.d.aqrl a0, a2, (a1)`e6c5b52f2f b5 c5 e6
Floating point
flw	`rd, imm12(rs1)`	Load a single-precision value into an FP register.	F
31–20imm[11:0]000000001000 19–15rs100010 14–120 1 0 11–7rd01010 6–00 0 0 0 1 1 1 Example`flw fa0, 8(sp)`0081250707 25 81 00
fsw	`rs2, imm12(rs1)`	Store a single-precision FP register.	F
31–25imm[11:5]0000000 24–20rs201010 19–15rs100010 14–120 1 0 11–7imm[4:0]01000 6–00 1 0 0 1 1 1 Example`fsw fa0, 8(sp)`00a1242727 24 a1 00
fmadd.s	`rd, rs1, rs2, rs3`	Fused multiply-add, single rounding: rd = (rs1 × rs2) + rs3.	F
31–27rs301101 26–250 0 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 0 0 0 1 1 Example`fmadd.s fa0, fa1, fa2, fa3`68c5f54343 f5 c5 68
fmsub.s	`rd, rs1, rs2, rs3`	Fused multiply-add, single rounding: rd = (rs1 × rs2) - rs3.	F
31–27rs301101 26–250 0 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 0 0 1 1 1 Example`fmsub.s fa0, fa1, fa2, fa3`68c5f54747 f5 c5 68
fnmsub.s	`rd, rs1, rs2, rs3`	Fused multiply-add, single rounding: rd = -(rs1 × rs2) + rs3.	F
31–27rs301101 26–250 0 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 0 1 0 1 1 Example`fnmsub.s fa0, fa1, fa2, fa3`68c5f54b4b f5 c5 68
fnmadd.s	`rd, rs1, rs2, rs3`	Fused multiply-add, single rounding: rd = -(rs1 × rs2) - rs3.	F
31–27rs301101 26–250 0 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 0 1 1 1 1 Example`fnmadd.s fa0, fa1, fa2, fa3`68c5f54f4f f5 c5 68
fadd.s	`rd, rs1, rs2`	Rd = rs1 + rs2 (single precision).	F
31–250 0 0 0 0 0 0 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 The `rm` field selects the rounding mode; 111 (dyn) uses `frm` in `fcsr`. Example`fadd.s fa0, fa1, fa2`00c5f55353 f5 c5 00
fsub.s	`rd, rs1, rs2`	Rd = rs1 - rs2 (single precision).	F
31–250 0 0 0 1 0 0 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fsub.s fa0, fa1, fa2`08c5f55353 f5 c5 08
fmul.s	`rd, rs1, rs2`	Rd = rs1 × rs2 (single precision).	F
31–250 0 0 1 0 0 0 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmul.s fa0, fa1, fa2`10c5f55353 f5 c5 10
fdiv.s	`rd, rs1, rs2`	Rd = rs1 / rs2 (single precision).	F
31–250 0 0 1 1 0 0 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fdiv.s fa0, fa1, fa2`18c5f55353 f5 c5 18
fsqrt.s	`rd, rs1`	Square root.	F
31–250 1 0 1 1 0 0 24–200 0 0 0 0 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fsqrt.s fa0, fa1`5805f55353 f5 05 58
fsgnj.s	`rd, rs1, rs2`	Magnitude of rs1 with the sign of rs2.	F
31–250 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 `fmv.s rd, rs` is `fsgnj.s rd, rs, rs`. Example`fsgnj.s fa0, fa1, fa2`20c5855353 85 c5 20
fsgnjn.s	`rd, rs1, rs2`	Magnitude of rs1 with the inverted sign of rs2.	F
31–250 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–01 0 1 0 0 1 1 `fneg.s rd, rs` is `fsgnjn.s rd, rs, rs`. Example`fsgnjn.s fa0, fa1, fa2`20c5955353 95 c5 20
fsgnjx.s	`rd, rs1, rs2`	Magnitude of rs1, sign = sign(rs1) XOR sign(rs2).	F
31–250 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–01 0 1 0 0 1 1 `fabs.s rd, rs` is `fsgnjx.s rd, rs, rs`. Example`fsgnjx.s fa0, fa1, fa2`20c5a55353 a5 c5 20
fmin.s	`rd, rs1, rs2`	Minimum (a NaN operand is ignored if the other is a number).	F
31–250 0 1 0 1 0 0 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmin.s fa0, fa1, fa2`28c5855353 85 c5 28
fmax.s	`rd, rs1, rs2`	Maximum.	F
31–250 0 1 0 1 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmax.s fa0, fa1, fa2`28c5955353 95 c5 28
feq.s	`rd, rs1, rs2`	Integer rd = 1 if rs1 == rs2 (quiet comparison).	F
31–251 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`feq.s a0, fa1, fa2`a0c5a55353 a5 c5 a0
flt.s	`rd, rs1, rs2`	Integer rd = 1 if rs1 < rs2.	F
31–251 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–01 0 1 0 0 1 1 Example`flt.s a0, fa1, fa2`a0c5955353 95 c5 a0
fle.s	`rd, rs1, rs2`	Integer rd = 1 if rs1 ≤ rs2.	F
31–251 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`fle.s a0, fa1, fa2`a0c5855353 85 c5 a0
fclass.s	`rd, rs1`	Write a 10-bit one-hot mask classifying rs1 (±inf, normal, subnormal, zero, NaN).	F
31–251 1 1 0 0 0 0 24–200 0 0 0 0 19–15rs101011 14–120 0 1 11–7rd01010 6–01 0 1 0 0 1 1 Example`fclass.s a0, fa1`e005955353 95 05 e0
fcvt.w.s	`rd, rs1`	Convert single-precision to signed 32-bit integer.	F
31–251 1 0 0 0 0 0 24–200 0 0 0 0 19–15rs101011 14–12rm001 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.w.s a0, fa1, rtz`c005955353 95 05 c0
fcvt.s.w	`rd, rs1`	Convert a signed 32-bit integer to single precision.	F
31–251 1 0 1 0 0 0 24–200 0 0 0 0 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.s.w fa0, a1`d005f55353 f5 05 d0
fcvt.wu.s	`rd, rs1`	Convert single-precision to unsigned 32-bit integer.	F
31–251 1 0 0 0 0 0 24–200 0 0 0 1 19–15rs101011 14–12rm001 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.wu.s a0, fa1, rtz`c015955353 95 15 c0
fcvt.s.wu	`rd, rs1`	Convert a unsigned 32-bit integer to single precision.	F
31–251 1 0 1 0 0 0 24–200 0 0 0 1 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.s.wu fa0, a1`d015f55353 f5 15 d0
fcvt.l.s	`rd, rs1`	Convert single-precision to signed 64-bit integer.	RV64F
31–251 1 0 0 0 0 0 24–200 0 0 1 0 19–15rs101011 14–12rm001 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.l.s a0, fa1, rtz`c025955353 95 25 c0
fcvt.s.l	`rd, rs1`	Convert a signed 64-bit integer to single precision.	RV64F
31–251 1 0 1 0 0 0 24–200 0 0 1 0 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.s.l fa0, a1`d025f55353 f5 25 d0
fcvt.lu.s	`rd, rs1`	Convert single-precision to unsigned 64-bit integer.	RV64F
31–251 1 0 0 0 0 0 24–200 0 0 1 1 19–15rs101011 14–12rm001 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.lu.s a0, fa1, rtz`c035955353 95 35 c0
fcvt.s.lu	`rd, rs1`	Convert a unsigned 64-bit integer to single precision.	RV64F
31–251 1 0 1 0 0 0 24–200 0 0 1 1 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.s.lu fa0, a1`d035f55353 f5 35 d0
fld	`rd, imm12(rs1)`	Load a double-precision value into an FP register.	D
31–20imm[11:0]000000001000 19–15rs100010 14–120 1 1 11–7rd01010 6–00 0 0 0 1 1 1 Example`fld fa0, 8(sp)`0081350707 35 81 00
fsd	`rs2, imm12(rs1)`	Store a double-precision FP register.	D
31–25imm[11:5]0000000 24–20rs201010 19–15rs100010 14–120 1 1 11–7imm[4:0]01000 6–00 1 0 0 1 1 1 Example`fsd fa0, 8(sp)`00a1342727 34 a1 00
fmadd.d	`rd, rs1, rs2, rs3`	Fused multiply-add, single rounding: rd = (rs1 × rs2) + rs3.	D
31–27rs301101 26–250 1 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 0 0 0 1 1 Example`fmadd.d fa0, fa1, fa2, fa3`6ac5f54343 f5 c5 6a
fmsub.d	`rd, rs1, rs2, rs3`	Fused multiply-add, single rounding: rd = (rs1 × rs2) - rs3.	D
31–27rs301101 26–250 1 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 0 0 1 1 1 Example`fmsub.d fa0, fa1, fa2, fa3`6ac5f54747 f5 c5 6a
fnmsub.d	`rd, rs1, rs2, rs3`	Fused multiply-add, single rounding: rd = -(rs1 × rs2) + rs3.	D
31–27rs301101 26–250 1 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 0 1 0 1 1 Example`fnmsub.d fa0, fa1, fa2, fa3`6ac5f54b4b f5 c5 6a
fnmadd.d	`rd, rs1, rs2, rs3`	Fused multiply-add, single rounding: rd = -(rs1 × rs2) - rs3.	D
31–27rs301101 26–250 1 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 0 1 1 1 1 Example`fnmadd.d fa0, fa1, fa2, fa3`6ac5f54f4f f5 c5 6a
fadd.d	`rd, rs1, rs2`	Rd = rs1 + rs2 (double precision).	D
31–250 0 0 0 0 0 1 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fadd.d fa0, fa1, fa2`02c5f55353 f5 c5 02
fsub.d	`rd, rs1, rs2`	Rd = rs1 - rs2 (double precision).	D
31–250 0 0 0 1 0 1 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fsub.d fa0, fa1, fa2`0ac5f55353 f5 c5 0a
fmul.d	`rd, rs1, rs2`	Rd = rs1 × rs2 (double precision).	D
31–250 0 0 1 0 0 1 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmul.d fa0, fa1, fa2`12c5f55353 f5 c5 12
fdiv.d	`rd, rs1, rs2`	Rd = rs1 / rs2 (double precision).	D
31–250 0 0 1 1 0 1 24–20rs201100 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fdiv.d fa0, fa1, fa2`1ac5f55353 f5 c5 1a
fsqrt.d	`rd, rs1`	Square root.	D
31–250 1 0 1 1 0 1 24–200 0 0 0 0 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fsqrt.d fa0, fa1`5a05f55353 f5 05 5a
fsgnj.d	`rd, rs1, rs2`	Magnitude of rs1 with the sign of rs2.	D
31–250 0 1 0 0 0 1 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 `fmv.d rd, rs` is `fsgnj.d rd, rs, rs`. Example`fsgnj.d fa0, fa1, fa2`22c5855353 85 c5 22
fsgnjn.d	`rd, rs1, rs2`	Magnitude of rs1 with the inverted sign of rs2.	D
31–250 0 1 0 0 0 1 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–01 0 1 0 0 1 1 `fneg.d rd, rs` is `fsgnjn.d rd, rs, rs`. Example`fsgnjn.d fa0, fa1, fa2`22c5955353 95 c5 22
fsgnjx.d	`rd, rs1, rs2`	Magnitude of rs1, sign = sign(rs1) XOR sign(rs2).	D
31–250 0 1 0 0 0 1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–01 0 1 0 0 1 1 `fabs.d rd, rs` is `fsgnjx.d rd, rs, rs`. Example`fsgnjx.d fa0, fa1, fa2`22c5a55353 a5 c5 22
fmin.d	`rd, rs1, rs2`	Minimum (a NaN operand is ignored if the other is a number).	D
31–250 0 1 0 1 0 1 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmin.d fa0, fa1, fa2`2ac5855353 85 c5 2a
fmax.d	`rd, rs1, rs2`	Maximum.	D
31–250 0 1 0 1 0 1 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmax.d fa0, fa1, fa2`2ac5955353 95 c5 2a
feq.d	`rd, rs1, rs2`	Integer rd = 1 if rs1 == rs2 (quiet comparison).	D
31–251 0 1 0 0 0 1 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`feq.d a0, fa1, fa2`a2c5a55353 a5 c5 a2
flt.d	`rd, rs1, rs2`	Integer rd = 1 if rs1 < rs2.	D
31–251 0 1 0 0 0 1 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–01 0 1 0 0 1 1 Example`flt.d a0, fa1, fa2`a2c5955353 95 c5 a2
fle.d	`rd, rs1, rs2`	Integer rd = 1 if rs1 ≤ rs2.	D
31–251 0 1 0 0 0 1 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`fle.d a0, fa1, fa2`a2c5855353 85 c5 a2
fclass.d	`rd, rs1`	Write a 10-bit one-hot mask classifying rs1 (±inf, normal, subnormal, zero, NaN).	D
31–251 1 1 0 0 0 1 24–200 0 0 0 0 19–15rs101011 14–120 0 1 11–7rd01010 6–01 0 1 0 0 1 1 Example`fclass.d a0, fa1`e205955353 95 05 e2
fcvt.w.d	`rd, rs1`	Convert double-precision to signed 32-bit integer.	D
31–251 1 0 0 0 0 1 24–200 0 0 0 0 19–15rs101011 14–12rm001 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.w.d a0, fa1, rtz`c205955353 95 05 c2
fcvt.d.w	`rd, rs1`	Convert a signed 32-bit integer to double precision.	D
31–251 1 0 1 0 0 1 24–200 0 0 0 0 19–15rs101011 14–12rm000 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.d.w fa0, a1`d205855353 85 05 d2
fcvt.wu.d	`rd, rs1`	Convert double-precision to unsigned 32-bit integer.	D
31–251 1 0 0 0 0 1 24–200 0 0 0 1 19–15rs101011 14–12rm001 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.wu.d a0, fa1, rtz`c215955353 95 15 c2
fcvt.d.wu	`rd, rs1`	Convert a unsigned 32-bit integer to double precision.	D
31–251 1 0 1 0 0 1 24–200 0 0 0 1 19–15rs101011 14–12rm000 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.d.wu fa0, a1`d215855353 85 15 d2
fcvt.l.d	`rd, rs1`	Convert double-precision to signed 64-bit integer.	RV64D
31–251 1 0 0 0 0 1 24–200 0 0 1 0 19–15rs101011 14–12rm001 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.l.d a0, fa1, rtz`c225955353 95 25 c2
fcvt.d.l	`rd, rs1`	Convert a signed 64-bit integer to double precision.	RV64D
31–251 1 0 1 0 0 1 24–200 0 0 1 0 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.d.l fa0, a1`d225f55353 f5 25 d2
fcvt.lu.d	`rd, rs1`	Convert double-precision to unsigned 64-bit integer.	RV64D
31–251 1 0 0 0 0 1 24–200 0 0 1 1 19–15rs101011 14–12rm001 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.lu.d a0, fa1, rtz`c235955353 95 35 c2
fcvt.d.lu	`rd, rs1`	Convert a unsigned 64-bit integer to double precision.	RV64D
31–251 1 0 1 0 0 1 24–200 0 0 1 1 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.d.lu fa0, a1`d235f55353 f5 35 d2
fcvt.s.d	`rd, rs1`	Convert double to single precision.	D
31–250 1 0 0 0 0 0 24–200 0 0 0 1 19–15rs101011 14–12rm111 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.s.d fa0, fa1`4015f55353 f5 15 40
fcvt.d.s	`rd, rs1`	Convert single to double precision (exact).	D
31–250 1 0 0 0 0 1 24–200 0 0 0 0 19–15rs101011 14–12rm000 11–7rd01010 6–01 0 1 0 0 1 1 Example`fcvt.d.s fa0, fa1`4205855353 85 05 42
fmv.x.w	`rd, rs1`	Copy the raw 32 bits of an FP register to an integer register (sign-extended).	F
31–251 1 1 0 0 0 0 24–200 0 0 0 0 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmv.x.w a0, fa1`e005855353 85 05 e0
fmv.w.x	`rd, rs1`	Copy the low 32 bits of an integer register to an FP register (NaN-boxed).	F
31–251 1 1 1 0 0 0 24–200 0 0 0 0 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmv.w.x fa0, a1`f005855353 85 05 f0
fmv.x.d	`rd, rs1`	Copy the raw 64 bits of an FP register to an integer register.	RV64D
31–251 1 1 0 0 0 1 24–200 0 0 0 0 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmv.x.d a0, fa1`e205855353 85 05 e2
fmv.d.x	`rd, rs1`	Copy an integer register bit-for-bit into an FP register.	RV64D
31–251 1 1 1 0 0 1 24–200 0 0 0 0 19–15rs101011 14–120 0 0 11–7rd01010 6–01 0 1 0 0 1 1 Example`fmv.d.x fa0, a1`f205855353 85 05 f2
Bit manipulation
sh1add	`rd, rs1, rs2`	`rd = (rs1 << 1) + rs2`: index an array of 2-byte elements.	Zba
31–250 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`sh1add a0, a1, a2`20c5a53333 a5 c5 20
sh1add.uw	`rd, rs1, rs2`	`rd = (zext32(rs1) << 1) + rs2`.	Zba
31–250 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 1 0 11–7rd01010 6–00 1 1 1 0 1 1 Example`sh1add.uw a0, a1, a2`20c5a53b3b a5 c5 20
sh2add	`rd, rs1, rs2`	`rd = (rs1 << 2) + rs2`: index an array of 4-byte elements.	Zba
31–250 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`sh2add a0, a1, a2`20c5c53333 c5 c5 20
sh2add.uw	`rd, rs1, rs2`	`rd = (zext32(rs1) << 2) + rs2`.	Zba
31–250 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 0 11–7rd01010 6–00 1 1 1 0 1 1 Example`sh2add.uw a0, a1, a2`20c5c53b3b c5 c5 20
sh3add	`rd, rs1, rs2`	`rd = (rs1 << 3) + rs2`: index an array of 8-byte elements.	Zba
31–250 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–121 1 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`sh3add a0, a1, a2`20c5e53333 e5 c5 20
sh3add.uw	`rd, rs1, rs2`	`rd = (zext32(rs1) << 3) + rs2`.	Zba
31–250 0 1 0 0 0 0 24–20rs201100 19–15rs101011 14–121 1 0 11–7rd01010 6–00 1 1 1 0 1 1 Example`sh3add.uw a0, a1, a2`20c5e53b3b e5 c5 20
add.uw	`rd, rs1, rs2`	`rd = zext32(rs1) + rs2`.	Zba
31–250 0 0 0 1 0 0 24–20rs201100 19–15rs101011 14–120 0 0 11–7rd01010 6–00 1 1 1 0 1 1 `zext.w rd, rs` is `add.uw rd, rs, x0`. Example`add.uw a0, a1, a2`08c5853b3b 85 c5 08
slli.uw	`rd, rs1, shamt`	`rd = zext32(rs1) << shamt`.	Zba
31–260 0 0 0 1 0 25–20shamt000010 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 1 0 1 1 Example`slli.uw a0, a1, 2`0825951b1b 95 25 08
andn	`rd, rs1, rs2`	`rd = rs1 & ~rs2`.	Zbb
31–250 1 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 1 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`andn a0, a1, a2`40c5f53333 f5 c5 40
orn	`rd, rs1, rs2`	`rd = rs1 \| ~rs2`.	Zbb
31–250 1 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 1 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`orn a0, a1, a2`40c5e53333 e5 c5 40
xnor	`rd, rs1, rs2`	`rd = ~(rs1 ^ rs2)`.	Zbb
31–250 1 0 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`xnor a0, a1, a2`40c5c53333 c5 c5 40
clz	`rd, rs1`	Count leading zero bits (XLEN if rs1 is 0).	Zbb
31–200 1 1 0 0 0 0 0 0 0 0 0 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`clz a0, a1`6005951313 95 05 60
ctz	`rd, rs1`	Count trailing zero bits.	Zbb
31–200 1 1 0 0 0 0 0 0 0 0 1 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`ctz a0, a1`6015951313 95 15 60
cpop	`rd, rs1`	Population count (number of set bits).	Zbb
31–200 1 1 0 0 0 0 0 0 0 1 0 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`cpop a0, a1`6025951313 95 25 60
clzw	`rd, rs1`	Count leading zeros of the low 32 bits.	Zbb
31–200 1 1 0 0 0 0 0 0 0 0 0 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 1 0 1 1 Example`clzw a0, a1`6005951b1b 95 05 60
ctzw	`rd, rs1`	Count trailing zeros of the low 32 bits.	Zbb
31–200 1 1 0 0 0 0 0 0 0 0 1 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 1 0 1 1 Example`ctzw a0, a1`6015951b1b 95 15 60
cpopw	`rd, rs1`	Population count of the low 32 bits.	Zbb
31–200 1 1 0 0 0 0 0 0 0 1 0 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 1 0 1 1 Example`cpopw a0, a1`6025951b1b 95 25 60
max	`rd, rs1, rs2`	Signed maximum.	Zbb
31–250 0 0 0 1 0 1 24–20rs201100 19–15rs101011 14–121 1 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`max a0, a1, a2`0ac5e53333 e5 c5 0a
maxu	`rd, rs1, rs2`	Unsigned maximum.	Zbb
31–250 0 0 0 1 0 1 24–20rs201100 19–15rs101011 14–121 1 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`maxu a0, a1, a2`0ac5f53333 f5 c5 0a
min	`rd, rs1, rs2`	Signed minimum.	Zbb
31–250 0 0 0 1 0 1 24–20rs201100 19–15rs101011 14–121 0 0 11–7rd01010 6–00 1 1 0 0 1 1 Example`min a0, a1, a2`0ac5c53333 c5 c5 0a
minu	`rd, rs1, rs2`	Unsigned minimum.	Zbb
31–250 0 0 0 1 0 1 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`minu a0, a1, a2`0ac5d53333 d5 c5 0a
sext.b	`rd, rs1`	Sign-extend the low byte.	Zbb
31–200 1 1 0 0 0 0 0 0 1 0 0 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`sext.b a0, a1`6045951313 95 45 60
sext.h	`rd, rs1`	Sign-extend the low halfword.	Zbb
31–200 1 1 0 0 0 0 0 0 1 0 1 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`sext.h a0, a1`6055951313 95 55 60
zext.h	`rd, rs1`	Zero-extend the low halfword (RV64 encoding).	Zbb
31–200 0 0 0 1 0 0 0 0 0 0 0 19–15rs101011 14–121 0 0 11–7rd01010 6–00 1 1 1 0 1 1 Example`zext.h a0, a1`0805c53b3b c5 05 08
rol	`rd, rs1, rs2`	Rotate left by the low bits of rs2.	Zbb
31–250 1 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`rol a0, a1, a2`60c5953333 95 c5 60
ror	`rd, rs1, rs2`	Rotate right by the low bits of rs2.	Zbb
31–250 1 1 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`ror a0, a1, a2`60c5d53333 d5 c5 60
rori	`rd, rs1, shamt`	Rotate right by an immediate.	Zbb
31–260 1 1 0 0 0 25–20shamt001101 19–15rs101011 14–121 0 1 11–7rd01010 6–00 0 1 0 0 1 1 There is no `roli`: assemblers turn it into `rori` with XLEN - shamt. Example`rori a0, a1, 13`60d5d51313 d5 d5 60
rolw	`rd, rs1, rs2`	32-bit rotate left, result sign-extended.	Zbb
31–250 1 1 0 0 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–00 1 1 1 0 1 1 Example`rolw a0, a1, a2`60c5953b3b 95 c5 60
rorw	`rd, rs1, rs2`	32-bit rotate right, result sign-extended.	Zbb
31–250 1 1 0 0 0 0 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 1 0 1 1 Example`rorw a0, a1, a2`60c5d53b3b d5 c5 60
roriw	`rd, rs1, shamt`	32-bit rotate right by an immediate, result sign-extended.	Zbb
31–250 1 1 0 0 0 0 24–20shamt01101 19–15rs101011 14–121 0 1 11–7rd01010 6–00 0 1 1 0 1 1 Example`roriw a0, a1, 13`60d5d51b1b d5 d5 60
orc.b	`rd, rs1`	Each result byte is 0xff if the source byte is non-zero, else 0x00.	Zbb
31–200 0 1 0 1 0 0 0 0 1 1 1 19–15rs101011 14–121 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Used by optimized `strlen` / `memchr` to find a zero byte in a word. Example`orc.b a0, a1`2875d51313 d5 75 28
rev8	`rd, rs1`	Reverse the byte order (RV64 encoding): endianness swap.	Zbb
31–200 1 1 0 1 0 1 1 1 0 0 0 19–15rs101011 14–121 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`rev8 a0, a1`6b85d51313 d5 85 6b
bclr	`rd, rs1, rs2`	Clear bit rs2 of rs1.	Zbs
31–250 1 0 0 1 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`bclr a0, a1, a2`48c5953333 95 c5 48
bclri	`rd, rs1, shamt`	Clear bit shamt of rs1.	Zbs
31–260 1 0 0 1 0 25–20shamt000101 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`bclri a0, a1, 5`4855951313 95 55 48
bext	`rd, rs1, rs2`	Extract bit rs2 of rs1 into bit 0.	Zbs
31–250 1 0 0 1 0 0 24–20rs201100 19–15rs101011 14–121 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`bext a0, a1, a2`48c5d53333 d5 c5 48
bexti	`rd, rs1, shamt`	Extract bit shamt of rs1 into bit 0.	Zbs
31–260 1 0 0 1 0 25–20shamt000101 19–15rs101011 14–121 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`bexti a0, a1, 5`4855d51313 d5 55 48
binv	`rd, rs1, rs2`	Invert bit rs2 of rs1.	Zbs
31–250 1 1 0 1 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`binv a0, a1, a2`68c5953333 95 c5 68
binvi	`rd, rs1, shamt`	Invert bit shamt of rs1.	Zbs
31–260 1 1 0 1 0 25–20shamt000101 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`binvi a0, a1, 5`6855951313 95 55 68
bset	`rd, rs1, rs2`	Set bit rs2 of rs1.	Zbs
31–250 0 1 0 1 0 0 24–20rs201100 19–15rs101011 14–120 0 1 11–7rd01010 6–00 1 1 0 0 1 1 Example`bset a0, a1, a2`28c5953333 95 c5 28
bseti	`rd, rs1, shamt`	Set bit shamt of rs1.	Zbs
31–260 0 1 0 1 0 25–20shamt000101 19–15rs101011 14–120 0 1 11–7rd01010 6–00 0 1 0 0 1 1 Example`bseti a0, a1, 5`2855951313 95 55 28
Privileged
mret		Return from a machine-mode trap: pc = mepc, privilege restored from mstatus.MPP.	Priv
31–250 0 1 1 0 0 0 24–200 0 0 1 0 19–150 0 0 0 0 14–120 0 0 11–70 0 0 0 0 6–01 1 1 0 0 1 1 Example`mret`3020007373 00 20 30
sret		Return from a supervisor-mode trap: pc = sepc, privilege restored from sstatus.SPP.	Priv
31–250 0 0 1 0 0 0 24–200 0 0 1 0 19–150 0 0 0 0 14–120 0 0 11–70 0 0 0 0 6–01 1 1 0 0 1 1 Example`sret`1020007373 00 20 10
wfi		Wait for interrupt: hint that the hart can stall until an interrupt is pending.	Priv
31–250 0 0 1 0 0 0 24–200 0 1 0 1 19–150 0 0 0 0 14–120 0 0 11–70 0 0 0 0 6–01 1 1 0 0 1 1 Example`wfi`1050007373 00 50 10
sfence.vma	`rs1, rs2`	Flush address-translation caches. rs1 = virtual address (x0 = all), rs2 = ASID (x0 = all).	Priv
31–250 0 0 1 0 0 1 24–20rs201011 19–15rs101010 14–120 0 0 11–70 0 0 0 0 6–01 1 1 0 0 1 1 Required after changing page tables or `satp`. Example`sfence.vma a0, a1`12b5007373 00 b5 12
Compressed (16-bit)
c.addi4spn	`rd', sp, nzuimm`	rd' = sp + nzuimm (multiple of 4). Expands to `addi rd', sp, nzuimm`.	C
15–130 0 0 12–5nzuimm[5:4\|9:6\|2\|3]01000000 4–2rd'010 1–00 0 The all-zero halfword 0x0000 is defined as illegal, so jumping into zeroed memory traps. Example`c.addi4spn a0, sp, 16`080808 08
c.fld	`rd', uimm(rs1')`	Expands to `fld rd', uimm(rs1')`.	C
15–130 0 1 12–10uimm[5:3]001 9–7rs1'011 6–5uimm[7:6]00 4–2rd'010 1–00 0 Example`c.fld fa0, 8(a1)`258888 25
c.lw	`rd', uimm(rs1')`	Expands to `lw rd', uimm(rs1')`.	C
15–130 1 0 12–10uimm[5:3]000 9–7rs1'011 6–5uimm[2\|6]10 4–2rd'010 1–00 0 Example`c.lw a0, 4(a1)`41c8c8 41
c.ld	`rd', uimm(rs1')`	Expands to `ld rd', uimm(rs1')`.	C
15–130 1 1 12–10uimm[5:3]001 9–7rs1'011 6–5uimm[7:6]00 4–2rd'010 1–00 0 Example`c.ld a0, 8(a1)`658888 65
c.fsd	`rs2', uimm(rs1')`	Expands to `fsd rs2', uimm(rs1')`.	C
15–131 0 1 12–10uimm[5:3]001 9–7rs1'011 6–5uimm[7:6]00 4–2rs2'010 1–00 0 Example`c.fsd fa0, 8(a1)`a58888 a5
c.sw	`rs2', uimm(rs1')`	Expands to `sw rs2', uimm(rs1')`.	C
15–131 1 0 12–10uimm[5:3]000 9–7rs1'011 6–5uimm[2\|6]10 4–2rs2'010 1–00 0 Example`c.sw a0, 4(a1)`c1c8c8 c1
c.sd	`rs2', uimm(rs1')`	Expands to `sd rs2', uimm(rs1')`.	C
15–131 1 1 12–10uimm[5:3]001 9–7rs1'011 6–5uimm[7:6]00 4–2rs2'010 1–00 0 Example`c.sd a0, 8(a1)`e58888 e5
c.nop		No operation (`addi x0, x0, 0`). Encoding 0x0001.	C
15–130 0 0 120 11–70 0 0 0 0 6–20 0 0 0 0 1–00 1 Example`c.nop`000101 00
c.addi	`rd, nzimm`	Expands to `addi rd, rd, nzimm`.	C
15–130 0 0 12nzimm[5]1 11–7rd01010 6–2nzimm[4:0]11101 1–00 1 Example`c.addi a0, -3`157575 15
c.addiw	`rd, imm`	Expands to `addiw rd, rd, imm` (RV64).	C
15–130 0 1 12imm[5]0 11–7rd01010 6–2imm[4:0]00001 1–00 1 Example`c.addiw a0, 1`250505 25
c.li	`rd, imm`	Expands to `addi rd, x0, imm`.	C
15–130 1 0 12imm[5]0 11–7rd10001 6–2imm[4:0]11111 1–00 1 Example`c.li a7, 31`48fdfd 48
c.addi16sp	`sp, nzimm`	Expands to `addi sp, sp, nzimm` (multiple of 16): prologues and epilogues.	C
15–130 1 1 12nzimm[9]1 11–70 0 0 1 0 6–2nzimm[4\|6\|8:7\|5]01110 1–00 1 Example`c.addi16sp sp, -64`713939 71
c.lui	`rd, nzimm`	Expands to `lui rd, nzimm` (rd not x0/x2).	C
15–130 1 1 12nzimm[17]0 11–7rd01010 6–2nzimm[16:12]00001 1–00 1 Example`c.lui a0, 1`650505 65
c.srli	`rd', shamt`	Expands to `srli rd', rd', shamt`.	C
15–131 0 0 12shamt[5]0 11–100 0 9–7rd'010 6–2shamt[4:0]00011 1–00 1 Example`c.srli a0, 3`810d0d 81
c.srai	`rd', shamt`	Expands to `srai rd', rd', shamt`.	C
15–131 0 0 12shamt[5]0 11–100 1 9–7rd'010 6–2shamt[4:0]00011 1–00 1 Example`c.srai a0, 3`850d0d 85
c.andi	`rd', imm`	Expands to `andi rd', rd', imm`.	C
15–131 0 0 12imm[5]0 11–101 0 9–7rd'010 6–2imm[4:0]00111 1–00 1 Example`c.andi a0, 7`891d1d 89
c.sub	`rd', rs2'`	Expands to `sub rd', rd', rs2'`.	C
15–131 0 0 120 11–101 1 9–7rd'010 6–50 0 4–2rs2'011 1–00 1 Example`c.sub a0, a1`8d0d0d 8d
c.xor	`rd', rs2'`	Expands to `xor rd', rd', rs2'`.	C
15–131 0 0 120 11–101 1 9–7rd'010 6–50 1 4–2rs2'011 1–00 1 Example`c.xor a0, a1`8d2d2d 8d
c.or	`rd', rs2'`	Expands to `or rd', rd', rs2'`.	C
15–131 0 0 120 11–101 1 9–7rd'010 6–51 0 4–2rs2'011 1–00 1 Example`c.or a0, a1`8d4d4d 8d
c.and	`rd', rs2'`	Expands to `and rd', rd', rs2'`.	C
15–131 0 0 120 11–101 1 9–7rd'010 6–51 1 4–2rs2'011 1–00 1 Example`c.and a0, a1`8d6d6d 8d
c.subw	`rd', rs2'`	Expands to `subw rd', rd', rs2'`.	C
15–131 0 0 121 11–101 1 9–7rd'010 6–50 0 4–2rs2'011 1–00 1 Example`c.subw a0, a1`9d0d0d 9d
c.addw	`rd', rs2'`	Expands to `addw rd', rd', rs2'`.	C
15–131 0 0 121 11–101 1 9–7rd'010 6–50 1 4–2rs2'011 1–00 1 Example`c.addw a0, a1`9d2d2d 9d
c.j	`offset`	Expands to `jal x0, offset` (±2 KiB).	C
15–131 0 1 12–2imm[11\|4\|9:8\|10\|6\|7\|3:1\|5]00000100000 1–00 1 Example`c.j 64`a08181 a0
c.beqz	`rs1', offset`	Expands to `beq rs1', x0, offset` (±256 B).	C
15–131 1 0 12–10imm[8\|4:3]010 9–7rs1'010 6–2imm[7:6\|2:1\|5]00000 1–00 1 Example`c.beqz a0, 16`c90101 c9
c.bnez	`rs1', offset`	Expands to `bne rs1', x0, offset`.	C
15–131 1 1 12–10imm[8\|4:3]010 9–7rs1'010 6–2imm[7:6\|2:1\|5]00000 1–00 1 Example`c.bnez a0, 16`e90101 e9
c.slli	`rd, shamt`	Expands to `slli rd, rd, shamt`.	C
15–130 0 0 12shamt[5]0 11–7rd01010 6–2shamt[4:0]00011 1–01 0 Example`c.slli a0, 3`050e0e 05
c.fldsp	`rd, uimm(sp)`	Expands to `fld rd, uimm(sp)`.	C
15–130 0 1 12uimm[5]0 11–7rd01010 6–2uimm[4:3\|8:6]01000 1–01 0 Example`c.fldsp fa0, 8(sp)`252222 25
c.lwsp	`rd, uimm(sp)`	Expands to `lw rd, uimm(sp)`.	C
15–130 1 0 12uimm[5]0 11–7rd01010 6–2uimm[4:2\|7:6]00100 1–01 0 Example`c.lwsp a0, 4(sp)`451212 45
c.ldsp	`rd, uimm(sp)`	Expands to `ld rd, uimm(sp)`.	C
15–130 1 1 12uimm[5]0 11–7rd00001 6–2uimm[4:3\|8:6]01000 1–01 0 Example`c.ldsp ra, 8(sp)`60a2a2 60
c.jr	`rs1`	Expands to `jalr x0, 0(rs1)`. `c.jr ra` (0x8082) is the compressed `ret`.	C
15–131 0 0 120 11–7rs100001 6–20 0 0 0 0 1–01 0 Example`c.jr ra`808282 80
c.mv	`rd, rs2`	Expands to `add rd, x0, rs2`.	C
15–131 0 0 120 11–7rd01010 6–2rs201011 1–01 0 Example`c.mv a0, a1`852e2e 85
c.ebreak		Breakpoint (0x9002). Debuggers use it on targets with C.	C
15–131 0 0 121 11–70 0 0 0 0 6–20 0 0 0 0 1–01 0 Example`c.ebreak`900202 90
c.jalr	`rs1`	Expands to `jalr ra, 0(rs1)`.	C
15–131 0 0 121 11–7rs100101 6–20 0 0 0 0 1–01 0 Example`c.jalr t0`928282 92
c.add	`rd, rs2`	Expands to `add rd, rd, rs2`.	C
15–131 0 0 121 11–7rd01010 6–2rs201011 1–01 0 Example`c.add a0, a1`952e2e 95
c.fsdsp	`rs2, uimm(sp)`	Expands to `fsd rs2, uimm(sp)`.	C
15–131 0 1 12–7uimm[5:3\|8:6]001000 6–2rs201010 1–01 0 Example`c.fsdsp fa0, 8(sp)`a42a2a a4
c.swsp	`rs2, uimm(sp)`	Expands to `sw rs2, uimm(sp)`.	C
15–131 1 0 12–7uimm[5:2\|7:6]000100 6–2rs201010 1–01 0 Example`c.swsp a0, 4(sp)`c22a2a c2
c.sdsp	`rs2, uimm(sp)`	Expands to `sd rs2, uimm(sp)`.	C
15–131 1 1 12–7uimm[5:3\|8:6]001000 6–2rs200001 1–01 0 Example`c.sdsp ra, 8(sp)`e40606 e4

No instruction matches this filter.